Align addresses in the buffering code to STORAGE_ALIGN_MASK if the target has one.

The PP502x DMA controller can only deal with doing DMA to 16-byte-aligned
addresses because we have inadequate control over the cache to prevent
interference. Other targets may also *prefer* cacheline aligned DMAs to
reduce the number of cache operations required. Almost all disk reads in
buffering.c will now be suitably aligned, allowing DMA to be used on PP502x.

Original change from FS#9708 by Boris Gjenero (dreamlayers).


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24440 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 16 insertions, 0 deletions

diff --git a/firmware/export/config.h b/firmware/export/config.h
index f731fb5513..96fec57d7b 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -889,6 +889,22 @@ Lyre prototype 1 */
 
 #endif /* HAVE_USBSTACK */
 
+/* Storage alignment: the mask specifies a mask of bits which should be
+ * clear in addresses used for storage_{read,write}_sectors(). This is
+ * only relevant for buffers that will contain one or more whole sectors.
+ */ 
+
+/* PP502x DMA requires an alignment of at least 16 bytes */
+#ifdef HAVE_ATA_DMA
+#ifdef  CPU_PP502x
+#define STORAGE_ALIGN_MASK 15
+#endif
+#endif /* HAVE_ATA_DMA */
+
+/* by default no alignment is required */
+#ifndef STORAGE_ALIGN_MASK
+#define STORAGE_ALIGN_MASK 0
+#endif
 
 
 #endif /* __CONFIG_H__ */