summaryrefslogtreecommitdiff
path: root/firmware
diff options
context:
space:
mode:
authorRafaël Carré <rafael.carre@gmail.com>2010-06-07 16:23:21 +0000
committerRafaël Carré <rafael.carre@gmail.com>2010-06-07 16:23:21 +0000
commit9730755fc7ee675e345744a7afa49024748ddd32 (patch)
treeb2066bbe986805e259d05d15686072173dfb2cf9 /firmware
parent4eea33e27d5cb9d5e98d230581529a36a529151a (diff)
downloadrockbox-9730755fc7ee675e345744a7afa49024748ddd32.tar.gz
rockbox-9730755fc7ee675e345744a7afa49024748ddd32.zip
Remove CORELOCK_SWAP (unused since r16981)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26664 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/export/config.h5
-rw-r--r--firmware/export/thread.h44
2 files changed, 0 insertions, 49 deletions
diff --git a/firmware/export/config.h b/firmware/export/config.h
index e64ca4127f..9a5aa73ed9 100644
--- a/firmware/export/config.h
+++ b/firmware/export/config.h
@@ -793,7 +793,6 @@ Lyre prototype 1 */
793#define CORELOCK_NONE 0 793#define CORELOCK_NONE 0
794#define SW_CORELOCK 1 /* Mutual exclusion provided by a software algorithm 794#define SW_CORELOCK 1 /* Mutual exclusion provided by a software algorithm
795 and not a special semaphore instruction */ 795 and not a special semaphore instruction */
796#define CORELOCK_SWAP 2 /* A swap (exchange) instruction */
797 796
798#if defined(CPU_PP) 797#if defined(CPU_PP)
799#define IDLE_STACK_SIZE 0x80 798#define IDLE_STACK_SIZE 0x80
@@ -818,11 +817,7 @@ Lyre prototype 1 */
818#define IF_COP_VOID(...) __VA_ARGS__ 817#define IF_COP_VOID(...) __VA_ARGS__
819#define IF_COP_CORE(core) core 818#define IF_COP_CORE(core) core
820 819
821#ifdef CPU_PP
822#define CONFIG_CORELOCK SW_CORELOCK /* SWP(B) is broken */ 820#define CONFIG_CORELOCK SW_CORELOCK /* SWP(B) is broken */
823#else
824#define CONFIG_CORELOCK CORELOCK_SWAP
825#endif
826 821
827#endif /* !defined(BOOTLOADER) && CONFIG_CPU != PP5002 */ 822#endif /* !defined(BOOTLOADER) && CONFIG_CPU != PP5002 */
828 823
diff --git a/firmware/export/thread.h b/firmware/export/thread.h
index 9678c0434f..f27557b3d4 100644
--- a/firmware/export/thread.h
+++ b/firmware/export/thread.h
@@ -175,21 +175,6 @@ void corelock_init(struct corelock *cl);
175void corelock_lock(struct corelock *cl); 175void corelock_lock(struct corelock *cl);
176int corelock_try_lock(struct corelock *cl); 176int corelock_try_lock(struct corelock *cl);
177void corelock_unlock(struct corelock *cl); 177void corelock_unlock(struct corelock *cl);
178#elif CONFIG_CORELOCK == CORELOCK_SWAP
179/* Use native atomic swap/exchange instruction */
180struct corelock
181{
182 volatile unsigned char locked;
183} __attribute__((packed));
184
185#define corelock_init(cl) \
186 ({ (cl)->locked = 0; })
187#define corelock_lock(cl) \
188 ({ while (test_and_set(&(cl)->locked, 1)); })
189#define corelock_try_lock(cl) \
190 ({ test_and_set(&(cl)->locked, 1) ? 0 : 1; })
191#define corelock_unlock(cl) \
192 ({ (cl)->locked = 0; })
193#else 178#else
194/* No atomic corelock op needed or just none defined */ 179/* No atomic corelock op needed or just none defined */
195#define corelock_init(cl) 180#define corelock_init(cl)
@@ -384,35 +369,6 @@ struct core_entry
384 *(a) = (v); \ 369 *(a) = (v); \
385 corelock_unlock(cl); \ 370 corelock_unlock(cl); \
386 o; }) 371 o; })
387#elif CONFIG_CORELOCK == CORELOCK_SWAP
388/* atomic */
389#define test_and_set(a, v, ...) \
390 xchg8((a), (v))
391#define xchg8(a, v, ...) \
392({ uint32_t o; \
393 asm volatile( \
394 "swpb %0, %1, [%2]" \
395 : "=&r"(o) \
396 : "r"(v), \
397 "r"((uint8_t*)(a))); \
398 o; })
399/* atomic */
400#define xchg32(a, v, ...) \
401({ uint32_t o; \
402 asm volatile( \
403 "swp %0, %1, [%2]" \
404 : "=&r"(o) \
405 : "r"((uint32_t)(v)), \
406 "r"((uint32_t*)(a))); \
407 o; })
408/* atomic */
409#define xchgptr(a, v, ...) \
410({ typeof (*(a)) o; \
411 asm volatile( \
412 "swp %0, %1, [%2]" \
413 : "=&r"(o) \
414 : "r"(v), "r"(a)); \
415 o; })
416#endif /* locking selection */ 372#endif /* locking selection */
417#elif defined (CPU_COLDFIRE) 373#elif defined (CPU_COLDFIRE)
418/* atomic */ 374/* atomic */