imx233: rewrite digctl using new register headers

Change-Id: I910a09e07b9f5a82bb6cb150739fcebc942cb7c1

2 files changed, 12 insertions, 39 deletions

diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 3bf6ebb0f7..8d705264bd 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -167,12 +167,8 @@ void udelay(unsigned us)
 
 void imx233_digctl_set_arm_cache_timings(unsigned timings)
 {
-    HW_DIGCTL_ARMCACHE =
-        timings << HW_DIGCTL_ARMCACHE__ITAG_SS_BP |
-        timings << HW_DIGCTL_ARMCACHE__DTAG_SS_BP |
-        timings << HW_DIGCTL_ARMCACHE__CACHE_SS_BP |
-        timings << HW_DIGCTL_ARMCACHE__DRTY_SS_BP |
-        timings << HW_DIGCTL_ARMCACHE__VALID_SS_BP;
+    HW_DIGCTL_ARMCACHE = BF_OR5(DIGCTL_ARMCACHE, ITAG_SS(timings),
+        DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
 }
 
 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
@@ -264,21 +260,23 @@ void set_cpu_frequency(long frequency)
 void imx233_enable_usb_controller(bool enable)
 {
     if(enable)
-        __REG_CLR(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE;
+        BF_CLR(DIGCTL_CTRL, USB_CLKGATE);
     else
-        __REG_SET(HW_DIGCTL_CTRL) = HW_DIGCTL_CTRL__USB_CLKGATE;
+        BF_SET(DIGCTL_CTRL, USB_CLKGATE);
 }
 
 void imx233_enable_usb_phy(bool enable)
 {
     if(enable)
     {
-        __REG_CLR(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
-        __REG_CLR(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL;
+        BF_CLR(USBPHY_CTRL, SFTRST);
+        BF_CLR(USBPHY_CTRL, CLKGATE);
+        HW_USBPHY_PWD_CLR = 0xffffffff;
     }
     else
     {
-        __REG_SET(HW_USBPHY_PWD) = HW_USBPHY_PWD__ALL;
-        __REG_SET(HW_USBPHY_CTRL) = __BLOCK_CLKGATE | __BLOCK_SFTRST;
+        HW_USBPHY_PWD_SET = 0xffffffff;
+        BF_SET(USBPHY_CTRL, SFTRST);
+        BF_SET(USBPHY_CTRL, CLKGATE);
     }
 }
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index c6073a9ae3..407369af7e 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -28,33 +28,8 @@
 #include "icoll-imx233.h"
 #include "clock-target.h" /* CPUFREQ_* are defined here */
 
-/* Digital control */
-#define HW_DIGCTL_BASE          0x8001C000
-#define HW_DIGCTL_CTRL          (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0))
-#define HW_DIGCTL_CTRL__USB_CLKGATE (1 << 2)
-
-#define HW_DIGCTL_HCLKCOUNT     (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x20))
-
-#define HW_DIGCTL_MICROSECONDS  (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0xC0))
-
-#define HW_DIGCTL_ARMCACHE      (*(volatile uint32_t *)(HW_DIGCTL_BASE + 0x2b0))
-#define HW_DIGCTL_ARMCACHE__ITAG_SS_BP  0
-#define HW_DIGCTL_ARMCACHE__ITAG_SS_BM  (3 << 0)
-#define HW_DIGCTL_ARMCACHE__DTAG_SS_BP  4
-#define HW_DIGCTL_ARMCACHE__DTAG_SS_BM  (3 << 4)
-#define HW_DIGCTL_ARMCACHE__CACHE_SS_BP  8
-#define HW_DIGCTL_ARMCACHE__CACHE_SS_BM  (3 << 8)
-#define HW_DIGCTL_ARMCACHE__DRTY_SS_BP  12
-#define HW_DIGCTL_ARMCACHE__DRTY_SS_BM  (3 << 12)
-#define HW_DIGCTL_ARMCACHE__VALID_SS_BP  16
-#define HW_DIGCTL_ARMCACHE__VALID_SS_BM  (3 << 16)
-
-/* USB Phy */
-#define HW_USBPHY_BASE          0x8007C000 
-#define HW_USBPHY_PWD           (*(volatile uint32_t *)(HW_USBPHY_BASE + 0))
-#define HW_USBPHY_PWD__ALL      (7 << 10 | 0xf << 17)
-
-#define HW_USBPHY_CTRL          (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
+#include "regs/regs-digctl.h"
+#include "regs/regs-usbphy.h"
 
 /**
  * Absolute maximum CPU speed: 454.74 MHz