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authorAmaury Pouly <amaury.pouly@gmail.com>2014-03-08 18:49:38 +0100
committerAmaury Pouly <amaury.pouly@gmail.com>2014-03-08 18:51:54 +0100
commit9637f4486b92cf70455aa4971ec7472aa4c1152d (patch)
treea2651c5e95341fc6f8e190ba0c503f9a7e484dbd /firmware
parent1f3979821c952a32ff4b9ca7ca229a8d78775bf9 (diff)
downloadrockbox-9637f4486b92cf70455aa4971ec7472aa4c1152d.tar.gz
rockbox-9637f4486b92cf70455aa4971ec7472aa4c1152d.zip
imx233: rewrite frequency scaling to use the new function
Change-Id: I0f9968de76ce17710d31f7bc609440654e68b6f1
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/arm/imx233/system-imx233.c24
1 files changed, 4 insertions, 20 deletions
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index ad88cba918..3cac826319 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -295,8 +295,6 @@ void imx233_set_cpu_frequency(long frequency)
295 return; 295 return;
296 /* disable auto-slow (enable back afterwards) */ 296 /* disable auto-slow (enable back afterwards) */
297 imx233_clkctrl_enable_auto_slow(false); 297 imx233_clkctrl_enable_auto_slow(false);
298 /* set VDDIO to the right value */
299 imx233_power_set_regulator(REGULATOR_VDDIO, 3300, 3125);
300 298
301 /* WARNING watch out the order ! */ 299 /* WARNING watch out the order ! */
302 if(frequency > cpu_frequency) 300 if(frequency > cpu_frequency)
@@ -305,29 +303,15 @@ void imx233_set_cpu_frequency(long frequency)
305 imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo); 303 imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
306 /* Change ARM cache timings */ 304 /* Change ARM cache timings */
307 imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings); 305 imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
308 /* Switch CPU to crystal at 24MHz */ 306 /* Change CPU and HBUS frequencies */
309 imx233_clkctrl_set_bypass(CLK_CPU, true); 307 imx233_clkctrl_set_cpu_hbus_div(prof->cpu_idiv, prof->cpu_fdiv, prof->hbus_div);
310 /* Program CPU divider for PLL */
311 imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
312 imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
313 /* Change the HBUS divider to its final value */
314 imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
315 /* Switch back CPU to PLL */
316 imx233_clkctrl_set_bypass(CLK_CPU, false);
317 /* Set the new EMI frequency */ 308 /* Set the new EMI frequency */
318 imx233_emi_set_frequency(prof->emi_freq); 309 imx233_emi_set_frequency(prof->emi_freq);
319 } 310 }
320 else 311 else
321 { 312 {
322 /* Switch CPU to crystal at 24MHz */ 313 /* Change CPU and HBUS frequencies */
323 imx233_clkctrl_set_bypass(CLK_CPU, true); 314 imx233_clkctrl_set_cpu_hbus_div(prof->cpu_idiv, prof->cpu_fdiv, prof->hbus_div);
324 /* Program HBUS divider to its final value */
325 imx233_clkctrl_set_div(CLK_HBUS, prof->hbus_div);
326 /* Program CPU divider for PLL */
327 imx233_clkctrl_set_frac_div(CLK_CPU, prof->cpu_fdiv);
328 imx233_clkctrl_set_div(CLK_CPU, prof->cpu_idiv);
329 /* Switch back CPU to PLL */
330 imx233_clkctrl_set_bypass(CLK_CPU, false);
331 /* Set the new EMI frequency */ 315 /* Set the new EMI frequency */
332 imx233_emi_set_frequency(prof->emi_freq); 316 imx233_emi_set_frequency(prof->emi_freq);
333 /* Change ARM cache timings */ 317 /* Change ARM cache timings */