summaryrefslogtreecommitdiff
path: root/firmware
diff options
context:
space:
mode:
authorMichael Sevakis <jethead71@rockbox.org>2011-08-28 07:45:35 +0000
committerMichael Sevakis <jethead71@rockbox.org>2011-08-28 07:45:35 +0000
commit7ad2cad173ffa094bb285112582afee1c9aea4e5 (patch)
treece23e816cfdffb1767ebe44f4f960c304d8a5fb9 /firmware
parent463b3ed8b2630d1b9d656dd2a52bbcbd429b4c08 (diff)
downloadrockbox-7ad2cad173ffa094bb285112582afee1c9aea4e5.tar.gz
rockbox-7ad2cad173ffa094bb285112582afee1c9aea4e5.zip
Commit work started in FS#12153 to put timing/position information in PCM
buffer chunks. * Samples and position indication is closely associated with audio data instead of compensating by a latency constant. Alleviates problems with using the elapsed as a track indicator where it could be off by several steps. * Timing is accurate throughout track even if resampling for pitch shift, whereas before it updated during transition latency at the normal 1:1 rate. * Simpler PCM buffer with a constant chunk size, no linked lists. In converting crossfade, a minor change was made to not change the WPS until the fade-in of the incoming track, whereas before it would change upon the start of the fade-out of the outgoing track possibly having the WPS change with far too much lead time. Codec changes are to set elapsed times *before* writing next PCM frame because time and position data last set are saved in the next committed PCM chunk. git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30366 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r--firmware/export/system.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/firmware/export/system.h b/firmware/export/system.h
index 5128801725..1f8ed033fd 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -378,12 +378,16 @@ static inline void cpucache_flush(void)
378#if defined(CPU_ARM) 378#if defined(CPU_ARM)
379 /* Use ARMs cache alignment. */ 379 /* Use ARMs cache alignment. */
380 #define MEM_ALIGN_ATTR CACHEALIGN_ATTR 380 #define MEM_ALIGN_ATTR CACHEALIGN_ATTR
381 #define MEM_ALIGN_SIZE CACHEALIGN_SIZE
381#elif defined(CPU_COLDFIRE) 382#elif defined(CPU_COLDFIRE)
382 /* Use fixed alignment of 16 bytes. Speed up only for 'movem' in DRAM. */ 383 /* Use fixed alignment of 16 bytes. Speed up only for 'movem' in DRAM. */
383 #define MEM_ALIGN_ATTR __attribute__((aligned(16))) 384 #define MEM_ALIGN_ATTR __attribute__((aligned(16)))
385 #define MEM_ALIGN_SIZE 16
384#else 386#else
385 /* Do nothing. */ 387 /* Do nothing. */
386 #define MEM_ALIGN_ATTR 388 #define MEM_ALIGN_ATTR
389 /* Align pointer size */
390 #define MEM_ALIGN_SIZE sizeof(intptr_t)
387#endif 391#endif
388 392
389#ifdef STORAGE_WANTS_ALIGN 393#ifdef STORAGE_WANTS_ALIGN