diff options
author | Michael Sevakis <jethead71@rockbox.org> | 2008-05-16 08:02:14 +0000 |
---|---|---|
committer | Michael Sevakis <jethead71@rockbox.org> | 2008-05-16 08:02:14 +0000 |
commit | 3c102ffd4d945ff332993546a920245bb2ce7333 (patch) | |
tree | 12ded927602f7235dce5c4dfde111248ce97c9a3 /firmware | |
parent | cda664b701dcd97c3a05ff1a5fdcfb88f9524761 (diff) | |
download | rockbox-3c102ffd4d945ff332993546a920245bb2ce7333.tar.gz rockbox-3c102ffd4d945ff332993546a920245bb2ce7333.zip |
Fix a couple mistakes. Forgot to add a few definitions.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17535 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/export/mc13783.h | 212 |
1 files changed, 205 insertions, 7 deletions
diff --git a/firmware/export/mc13783.h b/firmware/export/mc13783.h index c8cf67bedb..6ed1cb46be 100644 --- a/firmware/export/mc13783.h +++ b/firmware/export/mc13783.h | |||
@@ -393,10 +393,10 @@ enum mc13783_regs_enum | |||
393 | #define MC13783_VBKUP2EN (0x1 << 12) | 393 | #define MC13783_VBKUP2EN (0x1 << 12) |
394 | #define MC13783_VBKUP2AUTO (0x1 << 13) | 394 | #define MC13783_VBKUP2AUTO (0x1 << 13) |
395 | #define MC13783_VBKUP2 (0x3 << 14) | 395 | #define MC13783_VBKUP2 (0x3 << 14) |
396 | #define MC13783_VBKUP2_1_0V (0x0 << 10) | 396 | #define MC13783_VBKUP2_1_0V (0x0 << 14) |
397 | #define MC13783_VBKUP2_1_2V (0x1 << 10) | 397 | #define MC13783_VBKUP2_1_2V (0x1 << 14) |
398 | #define MC13783_VBKUP2_1_5V (0x2 << 10) | 398 | #define MC13783_VBKUP2_1_5V (0x2 << 14) |
399 | #define MC13783_VBKUP2_1_8V (0x3 << 10) | 399 | #define MC13783_VBKUP2_1_8V (0x3 << 14) |
400 | #define MC13783_BPDET (0x3 << 16) | 400 | #define MC13783_BPDET (0x3 << 16) |
401 | /* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */ | 401 | /* 00: UVDET 2.6, LOBATL UVDET+0.2, LOBATH UVDET+0.4 BPON 3.2 */ |
402 | #define MC13783_BPDET_2_4 (0x0 << 16) | 402 | #define MC13783_BPDET_2_4 (0x0 << 16) |
@@ -547,54 +547,172 @@ enum mc13783_regs_enum | |||
547 | 547 | ||
548 | /* SWITCHERS4 (28) */ | 548 | /* SWITCHERS4 (28) */ |
549 | #define MC13783_SW1AMODE (0x3 << 0) | 549 | #define MC13783_SW1AMODE (0x3 << 0) |
550 | #define MC13783_SW1AMODE_OFF (0x0 << 0) | ||
551 | #define MC13783_SW1AMODE_PWM (0x1 << 0) | ||
552 | #define MC13783_SW1AMODE_PWM_SKIP (0x2 << 0) | ||
553 | #define MC13783_SW1AMODE_PFM (0x3 << 0) | ||
550 | #define MC13783_SW1ASTBYMODE (0x3 << 2) | 554 | #define MC13783_SW1ASTBYMODE (0x3 << 2) |
555 | #define MC13783_SW1ASTBYMODE_OFF (0x0 << 2) | ||
556 | #define MC13783_SW1ASTBYMODE_PWM (0x1 << 2) | ||
557 | #define MC13783_SW1ASTBYMODE_PWM_SKIP (0x2 << 2) | ||
558 | #define MC13783_SW1ASTBYMODE_PFM (0x3 << 2) | ||
551 | #define MC13783_SW1ADVSSPEED (0x3 << 6) | 559 | #define MC13783_SW1ADVSSPEED (0x3 << 6) |
560 | /* 25mV every ... */ | ||
561 | #define MC13783_SW1ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6) | ||
562 | #define MC13783_SW1ADVSSPEED_4US (0x1 << 6) | ||
563 | #define MC13783_SW1ADVSSPEED_8US (0x2 << 6) | ||
564 | #define MC13783_SW1ADVSSPEED_16US (0x3 << 6) | ||
552 | #define MC13783_SW1APANIC (0x1 << 8) | 565 | #define MC13783_SW1APANIC (0x1 << 8) |
553 | #define MC13783_SW1ASFST (0x1 << 9) | 566 | #define MC13783_SW1ASFST (0x1 << 9) |
554 | #define MC13783_SW1BMODE (0x3 << 10) | 567 | #define MC13783_SW1BMODE (0x3 << 10) |
568 | #define MC13783_SW1BMODE_OFF (0x0 << 10) | ||
569 | #define MC13783_SW1BMODE_PWM (0x1 << 10) | ||
570 | #define MC13783_SW1BMODE_PWM_SKIP (0x2 << 10) | ||
571 | #define MC13783_SW1BMODE_PFM (0x3 << 10) | ||
555 | #define MC13783_SW1BSTBYMODE (0x3 << 12) | 572 | #define MC13783_SW1BSTBYMODE (0x3 << 12) |
573 | #define MC13783_SW1BSTBYMODE_OFF (0x0 << 12) | ||
574 | #define MC13783_SW1BSTBYMODE_PWM (0x1 << 12) | ||
575 | #define MC13783_SW1BSTBYMODE_PWM_SKIP (0x2 << 12) | ||
576 | #define MC13783_SW1BSTBYMODE_PFM (0x3 << 12) | ||
556 | #define MC13783_SW1BDVSSPEED (0x3 << 14) | 577 | #define MC13783_SW1BDVSSPEED (0x3 << 14) |
578 | /* 25mV every ... */ | ||
579 | #define MC13783_SW1BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14) | ||
580 | #define MC13783_SW1BDVSSPEED_4US (0x1 << 14) | ||
581 | #define MC13783_SW1BDVSSPEED_8US (0x2 << 14) | ||
582 | #define MC13783_SW1BDVSSPEED_16US (0x3 << 14) | ||
557 | #define MC13783_SW1BPANIC (0x1 << 16) | 583 | #define MC13783_SW1BPANIC (0x1 << 16) |
558 | #define MC13783_SW1BSFST (0x1 << 17) | 584 | #define MC13783_SW1BSFST (0x1 << 17) |
559 | #define MC13783_PLLEN (0x1 << 18) | 585 | #define MC13783_PLLEN (0x1 << 18) |
560 | #define MC13783_PLLX (0x7 << 19) | 586 | #define MC13783_PLLX (0x7 << 19) |
587 | #define MC13783_PLLX_28 (0x0 << 19) | ||
588 | #define MC13783_PLLX_29 (0x1 << 19) | ||
589 | #define MC13783_PLLX_30 (0x2 << 19) | ||
590 | #define MC13783_PLLX_31 (0x3 << 19) | ||
591 | #define MC13783_PLLX_32 (0x4 << 19) | ||
592 | #define MC13783_PLLX_33 (0x5 << 19) | ||
593 | #define MC13783_PLLX_34 (0x6 << 19) | ||
594 | #define MC13783_PLLX_35 (0x7 << 19) | ||
561 | 595 | ||
562 | /* SWITCHERS5 (29) */ | 596 | /* SWITCHERS5 (29) */ |
563 | #define MC13783_SW2AMODE (0x3 << 0) | 597 | #define MC13783_SW2AMODE (0x3 << 0) |
598 | #define MC13783_SW2AMODE_OFF (0x0 << 0) | ||
599 | #define MC13783_SW2AMODE_PWM (0x1 << 0) | ||
600 | #define MC13783_SW2AMODE_PWM_SKIP (0x2 << 0) | ||
601 | #define MC13783_SW2AMODE_PFM (0x3 << 0) | ||
564 | #define MC13783_SW2ASTBYMODE (0x3 << 2) | 602 | #define MC13783_SW2ASTBYMODE (0x3 << 2) |
603 | #define MC13783_SW2ASTBYMODE_OFF (0x0 << 2) | ||
604 | #define MC13783_SW2ASTBYMODE_PWM (0x1 << 2) | ||
605 | #define MC13783_SW2ASTBYMODE_PWM_SKIP (0x2 << 2) | ||
606 | #define MC13783_SW2ASTBYMODE_PFM (0x3 << 2) | ||
565 | #define MC13783_SW2ADVSSPEED (0x3 << 6) | 607 | #define MC13783_SW2ADVSSPEED (0x3 << 6) |
608 | #define MC13783_SW2ADVSSPEED_4US_NO_PWR_RDY (0x0 << 6) | ||
609 | #define MC13783_SW2ADVSSPEED_4US (0x1 << 6) | ||
610 | #define MC13783_SW2ADVSSPEED_8US (0x2 << 6) | ||
611 | #define MC13783_SW2ADVSSPEED_16US (0x3 << 6) | ||
566 | #define MC13783_SW2APANIC (0x1 << 8) | 612 | #define MC13783_SW2APANIC (0x1 << 8) |
567 | #define MC13783_SW2ASFST (0x1 << 9) | 613 | #define MC13783_SW2ASFST (0x1 << 9) |
568 | #define MC13783_SW2BMODE (0x3 << 10) | 614 | #define MC13783_SW2BMODE (0x3 << 10) |
615 | #define MC13783_SW2BMODE_OFF (0x0 << 10) | ||
616 | #define MC13783_SW2BMODE_PWM (0x1 << 10) | ||
617 | #define MC13783_SW2BMODE_PWM_SKIP (0x2 << 10) | ||
618 | #define MC13783_SW2BMODE_PFM (0x3 << 10) | ||
569 | #define MC13783_SW2BSTBYMODE (0x3 << 12) | 619 | #define MC13783_SW2BSTBYMODE (0x3 << 12) |
620 | #define MC13783_SW2BSTBYMODE_OFF (0x0 << 12) | ||
621 | #define MC13783_SW2BSTBYMODE_PWM (0x1 << 12) | ||
622 | #define MC13783_SW2BSTBYMODE_PWM_SKIP (0x2 << 12) | ||
623 | #define MC13783_SW2BSTBYMODE_PFM (0x3 << 12) | ||
570 | #define MC13783_SW2BDVSSPEED (0x3 << 14) | 624 | #define MC13783_SW2BDVSSPEED (0x3 << 14) |
625 | #define MC13783_SW2BDVSSPEED_4US_NO_PWR_RDY (0x0 << 14) | ||
626 | #define MC13783_SW2BDVSSPEED_4US (0x1 << 14) | ||
627 | #define MC13783_SW2BDVSSPEED_8US (0x2 << 14) | ||
628 | #define MC13783_SW2BDVSSPEED_16US (0x3 << 14) | ||
571 | #define MC13783_SW2BPANIC (0x1 << 16) | 629 | #define MC13783_SW2BPANIC (0x1 << 16) |
572 | #define MC13783_SW2BSFST (0x1 << 17) | 630 | #define MC13783_SW2BSFST (0x1 << 17) |
573 | #define MC13783_SW3 (0x3 << 18) | 631 | #define MC13783_SW3 (0x3 << 18) |
574 | #define MC13783_SW3_PRI_VOL_BOTH_OP (0x0 << 18) | 632 | #define MC13783_SW3_5_0V (0x0 << 18) |
575 | #define MC13783_SW3_SEC_VOL_BOTH_OP (0x2 << 18) | 633 | /* 0x1...0x2 same as 0x0 */ |
576 | #define MC13783_SW3_PRI_ONLY (0x3 << 18) | 634 | #define MC13783_SW3_5_5V (0x3 << 18) |
577 | #define MC13783_SW3EN (0x1 << 20) | 635 | #define MC13783_SW3EN (0x1 << 20) |
578 | #define MC13783_SW3STBY (0x1 << 21) | 636 | #define MC13783_SW3STBY (0x1 << 21) |
579 | #define MC13783_SW3MODE (0x1 << 22) | 637 | #define MC13783_SW3MODE (0x1 << 22) |
580 | 638 | ||
581 | /* REGULATOR_SETTING0 (30) */ | 639 | /* REGULATOR_SETTING0 (30) */ |
582 | #define MC13783_VIOLO (0x3 << 2) | 640 | #define MC13783_VIOLO (0x3 << 2) |
641 | #define MC13783_VIOLO_1_20V (0x0 << 2) | ||
642 | #define MC13783_VIOLO_1_30V (0x1 << 2) | ||
643 | #define MC13783_VIOLO_1_50V (0x2 << 2) | ||
644 | #define MC13783_VIOLO_1_80V (0x3 << 2) | ||
583 | #define MC13783_VDIG (0x3 << 4) | 645 | #define MC13783_VDIG (0x3 << 4) |
646 | #define MC13783_VDIG_1_20V (0x0 << 4) | ||
647 | #define MC13783_VDIG_1_30V (0x1 << 4) | ||
648 | #define MC13783_VDIG_1_50V (0x2 << 4) | ||
649 | #define MC13783_VDIG_1_80V (0x3 << 4) | ||
584 | #define MC13783_VGEN (0x7 << 6) | 650 | #define MC13783_VGEN (0x7 << 6) |
651 | #define MC13783_VGEN_1_20V (0x0 << 6) | ||
652 | #define MC13783_VGEN_1_30V (0x1 << 6) | ||
653 | #define MC13783_VGEN_1_50V (0x2 << 6) | ||
654 | #define MC13783_VGEN_1_80V (0x3 << 6) | ||
655 | #define MC13783_VGEN_1_10V (0x4 << 6) | ||
656 | #define MC13783_VGEN_2_00V (0x5 << 6) | ||
657 | #define MC13783_VGEN_2_775V (0x6 << 6) | ||
658 | #define MC13783_VGEN_2_40V (0x7 << 6) | ||
585 | #define MC13783_VRFDIG (0x3 << 9) | 659 | #define MC13783_VRFDIG (0x3 << 9) |
660 | #define MC13783_VREFDIG_1_20V (0x0 << 9) | ||
661 | #define MC13783_VREFDIG_1_30V (0x1 << 9) | ||
662 | #define MC13783_VREFDIG_1_80V (0x2 << 9) | ||
663 | #define MC13783_VREFDIG_1_875V (0x3 << 9) | ||
586 | #define MC13783_VRFREF (0x3 << 11) | 664 | #define MC13783_VRFREF (0x3 << 11) |
665 | #define MC13783_VRFREF_2_475V (0x0 << 11) | ||
666 | #define MC13783_VRFREF_2_600V (0x1 << 11) | ||
667 | #define MC13783_VRFREF_2_700V (0x2 << 11) | ||
668 | #define MC13783_VRFREF_2_775V (0x3 << 11) | ||
587 | #define MC13783_VRFCP (0x1 << 13) | 669 | #define MC13783_VRFCP (0x1 << 13) |
588 | #define MC13783_VSIM (0x1 << 14) | 670 | #define MC13783_VSIM (0x1 << 14) |
589 | #define MC13783_VESIM (0x1 << 15) | 671 | #define MC13783_VESIM (0x1 << 15) |
590 | #define MC13783_VCAM (0x7 << 16) | 672 | #define MC13783_VCAM (0x7 << 16) |
673 | #define MC13783_VCAM_1_50V (0x0 << 16) | ||
674 | #define MC13783_VCAM_1_80V (0x1 << 16) | ||
675 | #define MC13783_VCAM_2_50V (0x2 << 16) | ||
676 | #define MC13783_VCAM_2_55V (0x3 << 16) | ||
677 | #define MC13783_VCAM_2_60V (0x4 << 16) | ||
678 | #define MC13783_VCAM_2_75V (0x5 << 16) | ||
679 | #define MC13783_VCAM_2_80V (0x6 << 16) | ||
680 | #define MC13783_VCAM_3_00V (0x7 << 16) | ||
591 | 681 | ||
592 | /* REGULATOR_SETTING1 (31) */ | 682 | /* REGULATOR_SETTING1 (31) */ |
593 | #define MC13783_VVIB (0x3 << 0) | 683 | #define MC13783_VVIB (0x3 << 0) |
684 | #define MC13783_VVIB_1_30V (0x0 << 0) | ||
685 | #define MC13783_VVIB_1_80V (0x1 << 0) | ||
686 | #define MC13783_VVIB_2_00V (0x2 << 0) | ||
687 | #define MC13783_VVIB_3_00V (0x3 << 0) | ||
594 | #define MC13783_VRF1 (0x3 << 2) | 688 | #define MC13783_VRF1 (0x3 << 2) |
689 | #define MC13783_VRF1_1_500V (0x0 << 2) | ||
690 | #define MC13783_VRF1_1_875V (0x1 << 2) | ||
691 | #define MC13783_VRF1_2_700V (0x2 << 2) | ||
692 | #define MC13783_VRF1_2_775V (0x3 << 2) | ||
595 | #define MC13783_VRF2 (0x3 << 4) | 693 | #define MC13783_VRF2 (0x3 << 4) |
694 | #define MC13783_VRF2_1_500V (0x0 << 4) | ||
695 | #define MC13783_VRF2_1_875V (0x1 << 4) | ||
696 | #define MC13783_VRF2_2_700V (0x2 << 4) | ||
697 | #define MC13783_VRF2_2_775V (0x3 << 4) | ||
596 | #define MC13783_VMMC1 (0x7 << 6) | 698 | #define MC13783_VMMC1 (0x7 << 6) |
699 | #define MC13783_VMMC1_1_60V (0x0 << 6) | ||
700 | #define MC13783_VMMC1_1_80V (0x1 << 6) | ||
701 | #define MC13783_VMMC1_2_00V (0x2 << 6) | ||
702 | #define MC13783_VMMC1_2_60V (0x3 << 6) | ||
703 | #define MC13783_VMMC1_2_70V (0x4 << 6) | ||
704 | #define MC13783_VMMC1_2_80V (0x5 << 6) | ||
705 | #define MC13783_VMMC1_2_90V (0x6 << 6) | ||
706 | #define MC13783_VMMC1_3_00V (0x7 << 6) | ||
597 | #define MC13783_VMMC2 (0x7 << 9) | 707 | #define MC13783_VMMC2 (0x7 << 9) |
708 | #define MC13783_VMMC2_1_60V (0x0 << 9) | ||
709 | #define MC13783_VMMC2_1_80V (0x1 << 9) | ||
710 | #define MC13783_VMMC2_2_00V (0x2 << 9) | ||
711 | #define MC13783_VMMC2_2_60V (0x3 << 9) | ||
712 | #define MC13783_VMMC2_2_70V (0x4 << 9) | ||
713 | #define MC13783_VMMC2_2_80V (0x5 << 9) | ||
714 | #define MC13783_VMMC2_2_90V (0x6 << 9) | ||
715 | #define MC13783_VMMC2_3_00V (0x7 << 9) | ||
598 | 716 | ||
599 | /* REGULATOR_MODE0 (32) */ | 717 | /* REGULATOR_MODE0 (32) */ |
600 | #define MC13783_VAUDIOEN (0x1 << 0) | 718 | #define MC13783_VAUDIOEN (0x1 << 0) |
@@ -689,13 +807,29 @@ enum mc13783_regs_enum | |||
689 | /* AUDIO_RX1 (37) */ | 807 | /* AUDIO_RX1 (37) */ |
690 | #define MC13783_PGARXEN (0x1 << 0) | 808 | #define MC13783_PGARXEN (0x1 << 0) |
691 | #define MC13783_PGARX (0xf << 1) | 809 | #define MC13783_PGARX (0xf << 1) |
810 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | ||
811 | #define MC13783_PGARXw(x) (((x) << 1) & MC13783_PGARX) | ||
812 | #define MC13783_PGARXr(x) (((x) & MC13783_PGARX) >> 1) | ||
692 | #define MC13783_PGASTEN (0x1 << 5) | 813 | #define MC13783_PGASTEN (0x1 << 5) |
693 | #define MC13783_PGAST (0xf << 6) | 814 | #define MC13783_PGAST (0xf << 6) |
815 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | ||
816 | #define MC13783_PGASTw(x) (((x) << 6) & MC13783_PGAST) | ||
817 | #define MC13783_PGASTr(x) (((x) & MC13783_PGAST) >> 6) | ||
694 | #define MC13783_ARXINEN (0x1 << 10) | 818 | #define MC13783_ARXINEN (0x1 << 10) |
695 | #define MC13783_ARXIN (0x1 << 11) | 819 | #define MC13783_ARXIN (0x1 << 11) |
696 | #define MC13783_PGARXIN (0xf << 12) | 820 | #define MC13783_PGARXIN (0xf << 12) |
821 | /* <=0010=-33dB...1101=0dB...1111=+6dB in 3dB steps */ | ||
822 | #define MC13783_PGARXINw(x) (((x) << 12) & MC13783_PGARXIN) | ||
823 | #define MC13783_PGARXINr(x) (((x) & MC13783_PGARXIN) >> 12) | ||
697 | #define MC13783_MONO (0x3 << 16) | 824 | #define MC13783_MONO (0x3 << 16) |
825 | #define MC13783_MONO_LR_INDEPENDENT (0x0 << 16) | ||
826 | #define MC13783_MONO_ST_OPPOSITE (0x1 << 16) | ||
827 | #define MC13783_MONO_ST_TO_MONO (0x2 << 16) | ||
828 | #define MC13783_MONO_MONO_OPPOSITE (0x3 << 16) | ||
698 | #define MC13783_BAL (0x7 << 18) | 829 | #define MC13783_BAL (0x7 << 18) |
830 | /* 000=-21dB...3dB steps...111=0dB: left or right */ | ||
831 | #define MC13783_BALw(x) (((x) << 18) & MC13783_BAL) | ||
832 | #define MC13783_BALr(x) (((x) & MC13783_BAL) >> 18) | ||
699 | #define MC13783_BALLR (0x1 << 21) | 833 | #define MC13783_BALLR (0x1 << 21) |
700 | 834 | ||
701 | /* AUDIO_TX (38) */ | 835 | /* AUDIO_TX (38) */ |
@@ -713,19 +847,55 @@ enum mc13783_regs_enum | |||
713 | #define MC13783_ATXOUTEN (0x1 << 12) | 847 | #define MC13783_ATXOUTEN (0x1 << 12) |
714 | #define MC13783_RXINREC (0x1 << 13) | 848 | #define MC13783_RXINREC (0x1 << 13) |
715 | #define MC13783_PGATXR (0x1f << 14) | 849 | #define MC13783_PGATXR (0x1f << 14) |
850 | /* 00000=-8dB...01000=0dB...11111=+23dB */ | ||
851 | #define MC13783_PGATXRw(x) (((x) << 14) & MC13783_PGATXR) | ||
852 | #define MC13783_PGATXRr(x) (((x) & MC13783_PGATXR) >> 14) | ||
716 | #define MC13783_PGATXL (0x1f << 19) | 853 | #define MC13783_PGATXL (0x1f << 19) |
854 | /* 00000=-8dB...01000=0dB...11111=+23dB */ | ||
855 | #define MC13783_PGATXLw(x) (((x) << 19) & MC13783_PGATXL) | ||
856 | #define MC13783_PGATXLr(x) (((x) & MC13783_PGATXL) >> 19) | ||
717 | 857 | ||
718 | /* SSI_NETWORK (39) */ | 858 | /* SSI_NETWORK (39) */ |
719 | #define MC13783_CDCTXRXSLOT (0x3 << 2) | 859 | #define MC13783_CDCTXRXSLOT (0x3 << 2) |
860 | #define MC13783_CDCTXRXSLOT_TS0 (0x0 << 2) | ||
861 | #define MC13783_CDCTXRXSLOT_TS1 (0x1 << 2) | ||
862 | #define MC13783_CDCTXRXSLOT_TS2 (0x2 << 2) | ||
863 | #define MC13783_CDCTXRXSLOT_TS3 (0x3 << 2) | ||
720 | #define MC13783_CDCTXSECSLOT (0x3 << 4) | 864 | #define MC13783_CDCTXSECSLOT (0x3 << 4) |
865 | #define MC13783_CDCTXSECSLOT_TS0 (0x0 << 4) | ||
866 | #define MC13783_CDCTXSECSLOT_TS1 (0x1 << 4) | ||
867 | #define MC13783_CDCTXSECSLOT_TS2 (0x2 << 4) | ||
868 | #define MC13783_CDCTXSECSLOT_TS3 (0x3 << 4) | ||
721 | #define MC13783_CDCRXSECSLOT (0x3 << 6) | 869 | #define MC13783_CDCRXSECSLOT (0x3 << 6) |
870 | #define MC13783_CDCRXSECSLOT_TS0 (0x0 << 6) | ||
871 | #define MC13783_CDCRXSECSLOT_TS1 (0x1 << 6) | ||
872 | #define MC13783_CDCRXSECSLOT_TS2 (0x2 << 6) | ||
873 | #define MC13783_CDCRXSECSLOT_TS3 (0x3 << 6) | ||
722 | #define MC13783_CDCRXSECGAIN (0x3 << 8) | 874 | #define MC13783_CDCRXSECGAIN (0x3 << 8) |
875 | /* -inf, -0dB, -6dB, -12dB */ | ||
876 | #define MC13783_CDCRXSECGAINw(x) (((x) << 8) & MC13783_CDCRXSECGAIN) | ||
877 | #define MC13783_CDCRXSECGAINr(x) (((x) & MC13783_CDCRXSECGAIN) >> 8) | ||
723 | #define MC13783_CDCSUMGAIN (0x1 << 10) | 878 | #define MC13783_CDCSUMGAIN (0x1 << 10) |
724 | #define MC13783_CDCFSDLY (0x1 << 11) | 879 | #define MC13783_CDCFSDLY (0x1 << 11) |
725 | #define MC13783_STDCSLOTS (0x3 << 12) | 880 | #define MC13783_STDCSLOTS (0x3 << 12) |
881 | #define MC13783_STDCSLOTS_8 (0x0 << 12) | ||
882 | #define MC13783_STDCSLOTS_LR6 (0x1 << 12) | ||
883 | #define MC13783_STDCSLOTS_LR2 (0x2 << 12) | ||
884 | #define MC13783_STDCSLOTS_LR (0x3 << 12) | ||
726 | #define MC13783_STDCRXSLOT (0x3 << 14) | 885 | #define MC13783_STDCRXSLOT (0x3 << 14) |
886 | #define MC13783_STDCRXSLOT_TS0_TS1 (0x0 << 14) | ||
887 | #define MC13783_STDCRXSLOT_TS2_TS3 (0x1 << 14) | ||
888 | #define MC13783_STDCRXSLOT_TS4_TS5 (0x2 << 14) | ||
889 | #define MC13783_STDCRXSLOT_TS6_TS7 (0x3 << 14) | ||
727 | #define MC13783_STDCRXSECSLOT (0x3 << 16) | 890 | #define MC13783_STDCRXSECSLOT (0x3 << 16) |
891 | #define MC13783_STDCRXSECSLOT_TS0_TS1 (0x0 << 16) | ||
892 | #define MC13783_STDCRXSECSLOT_TS2_TS3 (0x1 << 16) | ||
893 | #define MC13783_STDCRXSECSLOT_TS4_TS5 (0x2 << 16) | ||
894 | #define MC13783_STDCRXSECSLOT_TS6_TS7 (0x3 << 16) | ||
728 | #define MC13783_STDCRXSECGAIN (0x3 << 18) | 895 | #define MC13783_STDCRXSECGAIN (0x3 << 18) |
896 | /* -inf, -0dB, -6dB, -12dB */ | ||
897 | #define MC13783_STDCRXSECGAINw(x) (((x) << 8) & MC13783_STDCRXSECGAIN) | ||
898 | #define MC13783_STDCRXSECGAINr(x) (((x) & MC13783_STDCRXSECGAIN) >> 8) | ||
729 | #define MC13783_STDSUMGAIN (0x1 << 20) | 899 | #define MC13783_STDSUMGAIN (0x1 << 20) |
730 | 900 | ||
731 | /* AUDIO_CODEC (40) */ | 901 | /* AUDIO_CODEC (40) */ |
@@ -735,6 +905,8 @@ enum mc13783_regs_enum | |||
735 | #define MC13783_CDCBCLINV (0x1 << 3) | 905 | #define MC13783_CDCBCLINV (0x1 << 3) |
736 | #define MC13783_CDCFSINV (0x1 << 4) | 906 | #define MC13783_CDCFSINV (0x1 << 4) |
737 | #define MC13783_CDCFS (0x3 << 5) | 907 | #define MC13783_CDCFS (0x3 << 5) |
908 | #define MC13783_CDCFS_NET (0x1 << 5) | ||
909 | #define MC13783_CDCFS_I2S (0x2 << 5) | ||
738 | #define MC13783_CDCCLK (0x7 << 7) | 910 | #define MC13783_CDCCLK (0x7 << 7) |
739 | #define MC13783_CDCFS8K16K (0x1 << 10) | 911 | #define MC13783_CDCFS8K16K (0x1 << 10) |
740 | #define MC13783_CDCEN (0x1 << 11) | 912 | #define MC13783_CDCEN (0x1 << 11) |
@@ -755,13 +927,39 @@ enum mc13783_regs_enum | |||
755 | #define MC13783_STDCBCLINV (0x1 << 3) | 927 | #define MC13783_STDCBCLINV (0x1 << 3) |
756 | #define MC13783_STDCFSINV (0x1 << 4) | 928 | #define MC13783_STDCFSINV (0x1 << 4) |
757 | #define MC13783_STDCFS (0x3 << 5) | 929 | #define MC13783_STDCFS (0x3 << 5) |
930 | #define MC13783_STDCFS_NORMAL (0x0 << 5) | ||
931 | #define MC13783_STDCFS_NET (0x1 << 5) | ||
932 | #define MC13783_STDCFS_I2S (0x2 << 5) | ||
758 | #define MC13783_STDCCLK (0x7 << 7) | 933 | #define MC13783_STDCCLK (0x7 << 7) |
934 | /* Master */ | ||
935 | #define MC13783_STDCCLK_13_0MHZ (0x0 << 7) | ||
936 | #define MC13783_STDCCLK_15_36MHZ (0x1 << 7) | ||
937 | #define MC13783_STDCCLK_16_8MHZ (0x2 << 7) | ||
938 | #define MC13783_STDCCLK_26_0MHZ (0x4 << 7) | ||
939 | #define MC13783_STDCCLK_12_0MHZ (0x5 << 7) | ||
940 | #define MC13783_STDCCLK_3_6864MHZ (0x6 << 7) | ||
941 | #define MC13783_STDCCLK_33_6MHZ (0x7 << 7) | ||
942 | /* Slave */ | ||
943 | #define MC13783_STDCCLK_CLIMCL (0x5 << 7) | ||
944 | #define MC13783_STDCCLK_FS (0x6 << 7) | ||
945 | #define MC13783_STDCCLK_BCL (0x7 << 7) | ||
759 | #define MC13783_STDCFSDLYB (0x1 << 10) | 946 | #define MC13783_STDCFSDLYB (0x1 << 10) |
760 | #define MC13783_STDCEN (0x1 << 11) | 947 | #define MC13783_STDCEN (0x1 << 11) |
761 | #define MC13783_STDCCLKEN (0x1 << 12) | 948 | #define MC13783_STDCCLKEN (0x1 << 12) |
762 | #define MC13783_STDCRESET (0x1 << 15) | 949 | #define MC13783_STDCRESET (0x1 << 15) |
763 | #define MC13783_SPDIF (0x1 << 16) | 950 | #define MC13783_SPDIF (0x1 << 16) |
764 | #define MC13783_SR (0xf << 17) | 951 | #define MC13783_SR (0xf << 17) |
952 | #define MC13783_SR_8000 (0x0 << 17) | ||
953 | #define MC13783_SR_11025 (0x1 << 17) | ||
954 | #define MC13783_SR_12000 (0x2 << 17) | ||
955 | #define MC13783_SR_16000 (0x3 << 17) | ||
956 | #define MC13783_SR_22050 (0x4 << 17) | ||
957 | #define MC13783_SR_24000 (0x5 << 17) | ||
958 | #define MC13783_SR_32000 (0x6 << 17) | ||
959 | #define MC13783_SR_44100 (0x7 << 17) | ||
960 | #define MC13783_SR_48000 (0x8 << 17) | ||
961 | #define MC13783_SR_64000 (0x9 << 17) | ||
962 | #define MC13783_SR_96000 (0xa << 17) | ||
765 | 963 | ||
766 | /* ADC0 (43) */ | 964 | /* ADC0 (43) */ |
767 | #define MC13783_LICELLCON (0x1 << 0) | 965 | #define MC13783_LICELLCON (0x1 << 0) |