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author | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-18 21:29:17 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-18 21:29:17 +0000 |
commit | 169cd33b3707ecfaea288c67dd39e586da93d795 (patch) | |
tree | 9c55236a3425f1826556ffd2198e6b0c80a8ce54 /firmware | |
parent | 22bf64a999671ad22307cb8178c433ed0f7fbcea (diff) | |
download | rockbox-169cd33b3707ecfaea288c67dd39e586da93d795.tar.gz rockbox-169cd33b3707ecfaea288c67dd39e586da93d795.zip |
iAudio: working PLL settings
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9104 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware')
-rw-r--r-- | firmware/SOURCES | 1 | ||||
-rw-r--r-- | firmware/system.c | 3 | ||||
-rw-r--r-- | firmware/target/coldfire/iaudio/x5/system-x5.c | 82 |
3 files changed, 85 insertions, 1 deletions
diff --git a/firmware/SOURCES b/firmware/SOURCES index 0aa6224bf7..6b80c5ee17 100644 --- a/firmware/SOURCES +++ b/firmware/SOURCES | |||
@@ -210,5 +210,6 @@ target/coldfire/iaudio/x5/lcd-x5.c | |||
210 | target/coldfire/iaudio/x5/pcf50606-x5.c | 210 | target/coldfire/iaudio/x5/pcf50606-x5.c |
211 | target/coldfire/iaudio/x5/adc-x5.c | 211 | target/coldfire/iaudio/x5/adc-x5.c |
212 | target/coldfire/iaudio/x5/ata-x5.c | 212 | target/coldfire/iaudio/x5/ata-x5.c |
213 | target/coldfire/iaudio/x5/system-x5.c | ||
213 | #endif | 214 | #endif |
214 | #endif | 215 | #endif |
diff --git a/firmware/system.c b/firmware/system.c index ae60148416..ec7feb7a21 100644 --- a/firmware/system.c +++ b/firmware/system.c | |||
@@ -579,6 +579,7 @@ int system_memory_guard(int newmode) | |||
579 | return oldmode; | 579 | return oldmode; |
580 | } | 580 | } |
581 | 581 | ||
582 | #ifndef TARGET_TREE | ||
582 | #ifdef IRIVER_H100 | 583 | #ifdef IRIVER_H100 |
583 | #define MAX_REFRESH_TIMER 59 | 584 | #define MAX_REFRESH_TIMER 59 |
584 | #define NORMAL_REFRESH_TIMER 21 | 585 | #define NORMAL_REFRESH_TIMER 21 |
@@ -642,7 +643,7 @@ void set_cpu_frequency(long frequency) | |||
642 | break; | 643 | break; |
643 | } | 644 | } |
644 | } | 645 | } |
645 | 646 | #endif | |
646 | 647 | ||
647 | #elif CONFIG_CPU == SH7034 | 648 | #elif CONFIG_CPU == SH7034 |
648 | #include "led.h" | 649 | #include "led.h" |
diff --git a/firmware/target/coldfire/iaudio/x5/system-x5.c b/firmware/target/coldfire/iaudio/x5/system-x5.c new file mode 100644 index 0000000000..1d9293b5c5 --- /dev/null +++ b/firmware/target/coldfire/iaudio/x5/system-x5.c | |||
@@ -0,0 +1,82 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | #include "kernel.h" | ||
22 | #include "system.h" | ||
23 | #include "power.h" | ||
24 | #include "timer.h" | ||
25 | |||
26 | #define MAX_REFRESH_TIMER 59 | ||
27 | #define NORMAL_REFRESH_TIMER 21 | ||
28 | #define DEFAULT_REFRESH_TIMER 4 | ||
29 | |||
30 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); | ||
31 | void set_cpu_frequency(long frequency) | ||
32 | { | ||
33 | switch(frequency) | ||
34 | { | ||
35 | case CPUFREQ_MAX: | ||
36 | DCR = (0x8200 | DEFAULT_REFRESH_TIMER); | ||
37 | /* Refresh timer for bypass frequency */ | ||
38 | PLLCR &= ~1; /* Bypass mode */ | ||
39 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
40 | PLLCR = 0x13442045; | ||
41 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | ||
42 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | ||
43 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | ||
44 | This may take up to 10ms! */ | ||
45 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | ||
46 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | ||
47 | cpu_frequency = CPUFREQ_MAX; | ||
48 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
49 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ | ||
50 | break; | ||
51 | |||
52 | case CPUFREQ_NORMAL: | ||
53 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
54 | /* Refresh timer for bypass frequency */ | ||
55 | PLLCR &= ~1; /* Bypass mode */ | ||
56 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
57 | PLLCR = 0x16430045; | ||
58 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | ||
59 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
60 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | ||
61 | This may take up to 10ms! */ | ||
62 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | ||
63 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | ||
64 | cpu_frequency = CPUFREQ_NORMAL; | ||
65 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
66 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | ||
67 | break; | ||
68 | default: | ||
69 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
70 | /* Refresh timer for bypass frequency */ | ||
71 | PLLCR &= ~1; /* Bypass mode */ | ||
72 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | ||
73 | PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */ | ||
74 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | ||
75 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
76 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | ||
77 | cpu_frequency = CPUFREQ_DEFAULT; | ||
78 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
79 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | ||
80 | break; | ||
81 | } | ||
82 | } | ||