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authorSolomon Peachy <pizza@shaftnet.org>2020-10-15 13:22:51 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-10-15 13:30:48 -0400
commit0cde20fadb9aeeb8e724d76e51bce7580296621b (patch)
treeda9695975e4705d39fc4e048e60a9f9a73b82ed3 /firmware
parentd544ce46a78c834492ae1116cd1d1e47cb9d8cb0 (diff)
downloadrockbox-0cde20fadb9aeeb8e724d76e51bce7580296621b.tar.gz
rockbox-0cde20fadb9aeeb8e724d76e51bce7580296621b.zip
xduoox3: Disable the DAC's digital de-emphasis filter.
Whether or not this is correct depends on how the source material was mastered, digitized, and/or encoded. There is no setting appropriate for everything. Eventually I'd like to make this configurable, but I'd want to have it shared with more than one target first. Change-Id: I20a0eff4b3dc2517c33db49d4f72e85bf81d1ca6
Diffstat (limited to 'firmware')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/codec-jz4760.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
index b00b3fddef..5adc4232af 100644
--- a/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4760.c
@@ -203,7 +203,6 @@ void audiohw_set_frequency(int fsel)
203{ 203{
204 unsigned int pll1_speed; 204 unsigned int pll1_speed;
205 unsigned short mclk_div, bclk_div, func_mode; 205 unsigned short mclk_div, bclk_div, func_mode;
206 unsigned char dem = CS4398_DEM_NONE;
207 206
208 // bclk is 2,3,4,6,8,12 ONLY 207 // bclk is 2,3,4,6,8,12 ONLY
209 // mclk is 1..512 208 // mclk is 1..512
@@ -250,21 +249,18 @@ void audiohw_set_frequency(int fsel)
250 pll1_speed = 426000000/4; 249 pll1_speed = 426000000/4;
251 mclk_div = 52/4; 250 mclk_div = 52/4;
252 bclk_div = 4; 251 bclk_div = 4;
253 dem = CS4398_DEM_32000;
254 func_mode = 0; 252 func_mode = 0;
255 break; 253 break;
256 case HW_FREQ_44: // 2.8224 MHz 254 case HW_FREQ_44: // 2.8224 MHz
257 pll1_speed = 508000000 / 3; 255 pll1_speed = 508000000 / 3;
258 mclk_div = 45 / 3; 256 mclk_div = 45 / 3;
259 bclk_div = 4; 257 bclk_div = 4;
260 dem = CS4398_DEM_44100;
261 func_mode = 0; 258 func_mode = 0;
262 break; 259 break;
263 case HW_FREQ_48: // 3.072 MHz 260 case HW_FREQ_48: // 3.072 MHz
264 pll1_speed = 516000000/2/3; 261 pll1_speed = 516000000/2/3;
265 mclk_div = 42/2/3; 262 mclk_div = 42/2/3;
266 bclk_div = 4; 263 bclk_div = 4;
267 dem = CS4398_DEM_48000;
268 func_mode = 0; 264 func_mode = 0;
269 break; 265 break;
270 case HW_FREQ_64: // 4.096 MHz 266 case HW_FREQ_64: // 4.096 MHz
@@ -307,7 +303,7 @@ void audiohw_set_frequency(int fsel)
307 /* 0 = Single-Speed Mode (<50KHz); 303 /* 0 = Single-Speed Mode (<50KHz);
308 1 = Double-Speed Mode (50-100KHz); 304 1 = Double-Speed Mode (50-100KHz);
309 2 = Quad-Speed Mode; (100-200KHz) */ 305 2 = Quad-Speed Mode; (100-200KHz) */
310 cs4398_write_reg(CS4398_REG_MODECTL, (cs4398_read_reg(CS4398_REG_MODECTL) & ~(CS4398_FM_MASK|CS4398_DEM_MASK)) | func_mode | dem); 306 cs4398_write_reg(CS4398_REG_MODECTL, (cs4398_read_reg(CS4398_REG_MODECTL) & ~(CS4398_FM_MASK|CS4398_DEM_MASK)) | func_mode | CS4398_DEM_NONE);
311 if (func_mode == 2) 307 if (func_mode == 2)
312 cs4398_write_reg(CS4398_REG_MISC, cs4398_read_reg(CS4398_REG_MISC) | CS4398_MCLKDIV2); 308 cs4398_write_reg(CS4398_REG_MISC, cs4398_read_reg(CS4398_REG_MISC) | CS4398_MCLKDIV2);
313 else 309 else