Enable nocache sections using the linker. PP5022/4 must use SW_CORELOCK now with shared variables in DRAM (it seems swp(b) is at least partially broken on all PP or I'm doing something very wrong here :\). For core-shared data use SHAREDBSS/DATA_ATTR. NOCACHEBSS/DATA_ATTR is available whether or not single core is forced for static peripheral-DMA buffer allocation without use of the UNCACHED_ADDR macro in code and is likely useful on a non-PP target with a data cache (although not actually enabled in config.h and the .lds's in this commit).

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@16981 a1c6a512-1295-4272-9138-f99709370657

1 files changed, 3 insertions, 3 deletions

diff --git a/firmware/timer.c b/firmware/timer.c
index 23df271220..c803048744 100644
--- a/firmware/timer.c
+++ b/firmware/timer.c
@@ -25,12 +25,12 @@
 #include "logf.h"
 
 static int timer_prio = -1;
-void NOCACHEBSS_ATTR (*pfn_timer)(void) = NULL;      /* timer callback */
-void NOCACHEBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
+void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL;      /* timer callback */
+void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
 #ifdef CPU_COLDFIRE
 static int base_prescale;
 #elif defined CPU_PP || CONFIG_CPU == PNX0101
-static long NOCACHEBSS_ATTR cycles_new = 0;
+static long SHAREDBSS_ATTR cycles_new = 0;
 #endif
 
 /* interrupt handler */