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authorMichael Sevakis <jethead71@rockbox.org>2009-02-11 19:28:02 +0000
committerMichael Sevakis <jethead71@rockbox.org>2009-02-11 19:28:02 +0000
commit84f8b0be2c08a469a1b1d6237817dd7db9e76582 (patch)
treed0258f607295141b68a49df76582f46ad663cc64 /firmware/thread.c
parentcdecd9dfa84368147a3f1e9f56f7d9e118bebe9c (diff)
downloadrockbox-84f8b0be2c08a469a1b1d6237817dd7db9e76582.tar.gz
rockbox-84f8b0be2c08a469a1b1d6237817dd7db9e76582.zip
s3c2440 can use the generic ARM WFI which is much simpler. If there's any advantage to setting the IDLE bit for power consumption, it's possible to combine its use with the old core_sleep instead of using the loop waiting for idle to kick in. For now, go basic. Let GCC choose the register for MCR instead of forcing it to r0.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19978 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/thread.c')
-rw-r--r--firmware/thread.c43
1 files changed, 5 insertions, 38 deletions
diff --git a/firmware/thread.c b/firmware/thread.c
index ce78769d11..453fbf510a 100644
--- a/firmware/thread.c
+++ b/firmware/thread.c
@@ -744,48 +744,15 @@ static void core_thread_init(unsigned int core)
744} 744}
745#endif /* NUM_CORES */ 745#endif /* NUM_CORES */
746 746
747#elif CONFIG_CPU == S3C2440
748
749/*---------------------------------------------------------------------------
750 * Put core in a power-saving state if waking list wasn't repopulated.
751 *---------------------------------------------------------------------------
752 */
753static inline void core_sleep(void)
754{
755 /* FIQ also changes the CLKCON register so FIQ must be disabled
756 when changing it here */
757 asm volatile (
758 "mrs r0, cpsr \n"
759 "orr r2, r0, #0x40 \n" /* Disable FIQ */
760 "bic r0, r0, #0x80 \n" /* Prepare IRQ enable */
761 "msr cpsr_c, r2 \n"
762 "mov r1, #0x4c000000 \n" /* CLKCON = 0x4c00000c */
763 "ldr r2, [r1, #0xc] \n" /* Set IDLE bit */
764 "orr r2, r2, #4 \n"
765 "str r2, [r1, #0xc] \n"
766 "msr cpsr_c, r0 \n" /* Enable IRQ, restore FIQ */
767 "mov r2, #0 \n" /* wait for IDLE */
768 "1: \n"
769 "add r2, r2, #1 \n"
770 "cmp r2, #10 \n"
771 "bne 1b \n"
772 "orr r2, r0, #0xc0 \n" /* Disable IRQ, FIQ */
773 "msr cpsr_c, r2 \n"
774 "ldr r2, [r1, #0xc] \n" /* Reset IDLE bit */
775 "bic r2, r2, #4 \n"
776 "str r2, [r1, #0xc] \n"
777 "msr cpsr_c, r0 \n" /* Enable IRQ, restore FIQ */
778 : : : "r0", "r1", "r2");
779}
780#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) /* Single core only for now */ \ 747#elif defined(CPU_TCC780X) || defined(CPU_TCC77X) /* Single core only for now */ \
781|| CONFIG_CPU == IMX31L || CONFIG_CPU == DM320 || CONFIG_CPU == AS3525 748|| CONFIG_CPU == IMX31L || CONFIG_CPU == DM320 || CONFIG_CPU == AS3525 \
782/* Use the generic ARMv4/v5 wait for IRQ */ 749|| CONFIG_CPU == S3C2440
750/* Use the generic ARMv4/v5/v6 wait for IRQ */
783static inline void core_sleep(void) 751static inline void core_sleep(void)
784{ 752{
785 asm volatile ( 753 asm volatile (
786 "mov r0, #0 \n" 754 "mcr p15, 0, %0, c7, c0, 4" /* Wait for interrupt */
787 "mcr p15, 0, r0, c7, c0, 4 \n" /* Wait for interrupt */ 755 : : "r"(0)
788 : : : "r0"
789 ); 756 );
790 enable_irq(); 757 enable_irq();
791} 758}