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author | Linus Nielsen Feltzing <linus@haxx.se> | 2002-05-05 22:13:00 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2002-05-05 22:13:00 +0000 |
commit | 55fec178bc630e3a52f46bcd74bc1bf319a1bc1a (patch) | |
tree | 4849d745a901c65983ffbf18fb3f4c50773a1ee4 /firmware/test/i2c/main.c | |
parent | c62a0852c3dd48339b22b936d252287539637958 (diff) | |
download | rockbox-55fec178bc630e3a52f46bcd74bc1bf319a1bc1a.tar.gz rockbox-55fec178bc630e3a52f46bcd74bc1bf319a1bc1a.zip |
Failed attempt to use DMA
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@453 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/test/i2c/main.c')
-rw-r--r-- | firmware/test/i2c/main.c | 45 |
1 files changed, 32 insertions, 13 deletions
diff --git a/firmware/test/i2c/main.c b/firmware/test/i2c/main.c index 746f1c7355..b5aecec733 100644 --- a/firmware/test/i2c/main.c +++ b/firmware/test/i2c/main.c | |||
@@ -82,8 +82,8 @@ void setup_sci0(void) | |||
82 | /* Clear FER and PER */ | 82 | /* Clear FER and PER */ |
83 | SSR0 &= 0xe7; | 83 | SSR0 &= 0xe7; |
84 | 84 | ||
85 | /* Set interrupt D priority to 0 */ | 85 | /* Set interrupt ITU2 and SCI0 priority to 0 */ |
86 | // IPRD &= 0x0ff0; | 86 | IPRD &= 0x0ff0; |
87 | 87 | ||
88 | /* set IRQ6 and IRQ7 to edge detect */ | 88 | /* set IRQ6 and IRQ7 to edge detect */ |
89 | // ICR |= 0x03; | 89 | // ICR |= 0x03; |
@@ -98,7 +98,7 @@ void setup_sci0(void) | |||
98 | IPRB = 0; | 98 | IPRB = 0; |
99 | 99 | ||
100 | /* Enable Tx (only!) */ | 100 | /* Enable Tx (only!) */ |
101 | SCR0 |= 0x20; | 101 | SCR0 |= 0xa0; |
102 | } | 102 | } |
103 | 103 | ||
104 | int mas_tx_ready(void) | 104 | int mas_tx_ready(void) |
@@ -106,12 +106,32 @@ int mas_tx_ready(void) | |||
106 | return (SSR0 & SCI_TDRE); | 106 | return (SSR0 & SCI_TDRE); |
107 | } | 107 | } |
108 | 108 | ||
109 | void init_dma(void) | ||
110 | { | ||
111 | SAR3 = (unsigned int) mp3data; | ||
112 | DAR3 = 0xFFFFEC3; | ||
113 | CHCR3 = 0x1500; /* Single address destination, TXI0 */ | ||
114 | DTCR3 = 64000; | ||
115 | DMAOR = 0x0001; /* Enable DMA */ | ||
116 | } | ||
117 | |||
118 | void start_dma(void) | ||
119 | { | ||
120 | CHCR3 |= 1; | ||
121 | } | ||
122 | |||
123 | void stop_dma(void) | ||
124 | { | ||
125 | CHCR3 &= ~1; | ||
126 | } | ||
127 | |||
109 | 128 | ||
110 | int main(void) | 129 | int main(void) |
111 | { | 130 | { |
112 | char buf[40]; | 131 | char buf[40]; |
113 | char str[32]; | 132 | char str[32]; |
114 | int i=0; | 133 | int i=0; |
134 | int dma_on = 0; | ||
115 | 135 | ||
116 | /* Clear it all! */ | 136 | /* Clear it all! */ |
117 | SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER); | 137 | SSR1 &= ~(SCI_RDRF | SCI_ORER | SCI_PER | SCI_FER); |
@@ -217,11 +237,15 @@ int main(void) | |||
217 | 237 | ||
218 | i = 0; | 238 | i = 0; |
219 | 239 | ||
240 | init_dma(); | ||
241 | |||
220 | while(1) | 242 | while(1) |
221 | { | 243 | { |
222 | /* Demand pin high? */ | 244 | /* Demand pin high? */ |
223 | if(PBDR & 0x4000) | 245 | if(PBDR & 0x4000) |
224 | { | 246 | { |
247 | start_dma(); | ||
248 | #if 0 | ||
225 | /* More data to write? */ | 249 | /* More data to write? */ |
226 | if(i < mp3datalen) | 250 | if(i < mp3datalen) |
227 | { | 251 | { |
@@ -232,18 +256,13 @@ int main(void) | |||
232 | TDR0 = fliptable[mp3data[i++]]; | 256 | TDR0 = fliptable[mp3data[i++]]; |
233 | SSR0 &= ~SCI_TDRE; | 257 | SSR0 &= ~SCI_TDRE; |
234 | } | 258 | } |
259 | #endif | ||
260 | } | ||
261 | else | ||
262 | { | ||
263 | stop_dma(); | ||
235 | } | 264 | } |
236 | } | 265 | } |
237 | 266 | ||
238 | while(1); | 267 | while(1); |
239 | } | 268 | } |
240 | |||
241 | extern const void stack(void); | ||
242 | |||
243 | const void* vectors[] __attribute__ ((section (".vectors"))) = | ||
244 | { | ||
245 | main, /* Power-on reset */ | ||
246 | stack, /* Power-on reset (stack pointer) */ | ||
247 | main, /* Manual reset */ | ||
248 | stack /* Manual reset (stack pointer) */ | ||
249 | }; | ||