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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-06-07 17:35:40 +0100 |
---|---|---|
committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-07-10 15:22:10 +0100 |
commit | cc017f211a338a68a571226e589ce34e47fc8ad3 (patch) | |
tree | 6db04ff23a3069c33be297938adc634c34592d7c /firmware/target | |
parent | 131566b8f80355aa64bba904f9de4d1506b90442 (diff) | |
download | rockbox-cc017f211a338a68a571226e589ce34e47fc8ad3.tar.gz rockbox-cc017f211a338a68a571226e589ce34e47fc8ad3.zip |
x1000: support 2nd device ID byte for NAND flash
Some components have additional ID bytes. Add support for an
optional 2nd device ID byte during the identification routine.
Change-Id: I5bbad73fb57004067c6f13f223f7bf4d43ff7849
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 21 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.h | 4 |
2 files changed, 16 insertions, 9 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 18d548ba8c..382fd761b3 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -98,21 +98,24 @@ static bool identify_chip(nand_drv* drv) | |||
98 | * - 1 byte address, no dummy byte | 98 | * - 1 byte address, no dummy byte |
99 | * - no address byte, 1 byte dummy | 99 | * - no address byte, 1 byte dummy |
100 | * | 100 | * |
101 | * Right now there is only a need for the 2nd variation, as that is | 101 | * Currently we use the 2nd method, aka. address read ID. |
102 | * the method used by the ATO25D1GA. | ||
103 | * | ||
104 | * Some chips also output more than 2 ID bytes. | ||
105 | */ | 102 | */ |
106 | sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 2|SFC_READ); | 103 | sfc_exec(NANDCMD_READID(1, 0), 0, drv->scratch_buf, 4|SFC_READ); |
107 | drv->mf_id = drv->scratch_buf[0]; | 104 | drv->mf_id = drv->scratch_buf[0]; |
108 | drv->dev_id = drv->scratch_buf[1]; | 105 | drv->dev_id = drv->scratch_buf[1]; |
106 | drv->dev_id2 = drv->scratch_buf[2]; | ||
109 | 107 | ||
110 | for(size_t i = 0; i < nr_supported_nand_chips; ++i) { | 108 | for(size_t i = 0; i < nr_supported_nand_chips; ++i) { |
111 | const nand_chip* chip = &supported_nand_chips[i]; | 109 | const nand_chip* chip = &supported_nand_chips[i]; |
112 | if(chip->mf_id == drv->mf_id && chip->dev_id == drv->dev_id) { | 110 | if(chip->mf_id != drv->mf_id || chip->dev_id != drv->dev_id) |
113 | drv->chip = chip; | 111 | continue; |
114 | return true; | 112 | |
115 | } | 113 | if((chip->flags & NAND_CHIPFLAG_HAS_DEVID2) && |
114 | chip->dev_id2 != drv->dev_id2) | ||
115 | continue; | ||
116 | |||
117 | drv->chip = chip; | ||
118 | return true; | ||
116 | } | 119 | } |
117 | 120 | ||
118 | return false; | 121 | return false; |
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h index 5e6d1f09bc..176897e4f2 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.h +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h | |||
@@ -41,6 +41,8 @@ | |||
41 | #define NAND_CHIPFLAG_QUAD 0x0001 | 41 | #define NAND_CHIPFLAG_QUAD 0x0001 |
42 | /* Chip requires QE bit set to enable quad I/O mode */ | 42 | /* Chip requires QE bit set to enable quad I/O mode */ |
43 | #define NAND_CHIPFLAG_HAS_QE_BIT 0x0002 | 43 | #define NAND_CHIPFLAG_HAS_QE_BIT 0x0002 |
44 | /* Chip has 2nd device ID byte */ | ||
45 | #define NAND_CHIPFLAG_HAS_DEVID2 0x0004 | ||
44 | 46 | ||
45 | /* cmd mode a d phase format has data */ | 47 | /* cmd mode a d phase format has data */ |
46 | #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) | 48 | #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) |
@@ -97,6 +99,7 @@ typedef struct nand_chip { | |||
97 | /* Manufacturer and device ID bytes */ | 99 | /* Manufacturer and device ID bytes */ |
98 | uint8_t mf_id; | 100 | uint8_t mf_id; |
99 | uint8_t dev_id; | 101 | uint8_t dev_id; |
102 | uint8_t dev_id2; | ||
100 | 103 | ||
101 | /* Row/column address width */ | 104 | /* Row/column address width */ |
102 | uint8_t row_cycles; | 105 | uint8_t row_cycles; |
@@ -158,6 +161,7 @@ typedef struct nand_drv { | |||
158 | /* Probed mf_id / dev_id for debugging, in case identification fails. */ | 161 | /* Probed mf_id / dev_id for debugging, in case identification fails. */ |
159 | uint8_t mf_id; | 162 | uint8_t mf_id; |
160 | uint8_t dev_id; | 163 | uint8_t dev_id; |
164 | uint8_t dev_id2; | ||
161 | 165 | ||
162 | /* SFC commands used for I/O, these are set based on chip data */ | 166 | /* SFC commands used for I/O, these are set based on chip data */ |
163 | uint32_t cmd_page_read; | 167 | uint32_t cmd_page_read; |