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authorAmaury Pouly <amaury.pouly@gmail.com>2012-05-19 13:23:17 +0200
committerAmaury Pouly <amaury.pouly@gmail.com>2012-05-19 16:10:51 +0200
commit9ced006c06a4240cbd2a9ebe9196d9a0658810f9 (patch)
tree92f9bf71af3c76ba3b885cb372f0dc46d1482356 /firmware/target
parent553aeae9c63f789c969a954983e537244934903a (diff)
downloadrockbox-9ced006c06a4240cbd2a9ebe9196d9a0658810f9.tar.gz
rockbox-9ced006c06a4240cbd2a9ebe9196d9a0658810f9.zip
imx233: move icoll stuff to its own file
The icoll code now has an IRQ storm detection mechanism which will prevent the device from hard freezing in case it happen. Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/arm/imx233/dcp-imx233.c2
-rw-r--r--firmware/target/arm/imx233/i2c-imx233.c2
-rw-r--r--firmware/target/arm/imx233/icoll-imx233.c177
-rw-r--r--firmware/target/arm/imx233/icoll-imx233.h81
-rw-r--r--firmware/target/arm/imx233/pcm-imx233.c4
-rw-r--r--firmware/target/arm/imx233/pinctrl-imx233.c2
-rw-r--r--firmware/target/arm/imx233/power-imx233.c2
-rw-r--r--firmware/target/arm/imx233/ssp-imx233.c2
-rw-r--r--firmware/target/arm/imx233/system-imx233.c122
-rw-r--r--firmware/target/arm/imx233/system-target.h45
-rw-r--r--firmware/target/arm/imx233/timrot-imx233.c4
-rw-r--r--firmware/target/arm/imx233/usb-imx233.c2
12 files changed, 271 insertions, 174 deletions
diff --git a/firmware/target/arm/imx233/dcp-imx233.c b/firmware/target/arm/imx233/dcp-imx233.c
index f7849b183f..358441ef84 100644
--- a/firmware/target/arm/imx233/dcp-imx233.c
+++ b/firmware/target/arm/imx233/dcp-imx233.c
@@ -116,7 +116,7 @@ static enum imx233_dcp_error_t imx233_dcp_job(int ch)
116 /* if IRQs are not enabled, don't enable channel interrupt and do some polling */ 116 /* if IRQs are not enabled, don't enable channel interrupt and do some polling */
117 bool irq_enabled = irq_enabled(); 117 bool irq_enabled = irq_enabled();
118 /* enable channel, clear interrupt, enable interrupt */ 118 /* enable channel, clear interrupt, enable interrupt */
119 imx233_enable_interrupt(INT_SRC_DCP, true); 119 imx233_icoll_enable_interrupt(INT_SRC_DCP, true);
120 if(irq_enabled) 120 if(irq_enabled)
121 __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch); 121 __REG_SET(HW_DCP_CTRL) = HW_DCP_CTRL__CHANNEL_INTERRUPT_ENABLE(ch);
122 __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch); 122 __REG_CLR(HW_DCP_STAT) = HW_DCP_STAT__IRQ(ch);
diff --git a/firmware/target/arm/imx233/i2c-imx233.c b/firmware/target/arm/imx233/i2c-imx233.c
index 199ad181ba..c58494154f 100644
--- a/firmware/target/arm/imx233/i2c-imx233.c
+++ b/firmware/target/arm/imx233/i2c-imx233.c
@@ -124,7 +124,7 @@ enum imx233_i2c_error_t imx233_i2c_end(unsigned timeout)
124 i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT; 124 i2c_stage[i2c_nr_stages - 1].dma.cmd |= HW_APB_CHx_CMD__SEMAPHORE | HW_APB_CHx_CMD__IRQONCMPLT;
125 125
126 __REG_CLR(HW_I2C_CTRL1) = HW_I2C_CTRL1__ALL_IRQ; 126 __REG_CLR(HW_I2C_CTRL1) = HW_I2C_CTRL1__ALL_IRQ;
127 imx233_enable_interrupt(INT_SRC_I2C_DMA, true); 127 imx233_icoll_enable_interrupt(INT_SRC_I2C_DMA, true);
128 imx233_dma_enable_channel_interrupt(APB_I2C, true); 128 imx233_dma_enable_channel_interrupt(APB_I2C, true);
129 imx233_dma_reset_channel(APB_I2C); 129 imx233_dma_reset_channel(APB_I2C);
130 imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma); 130 imx233_dma_start_command(APB_I2C, &i2c_stage[0].dma);
diff --git a/firmware/target/arm/imx233/icoll-imx233.c b/firmware/target/arm/imx233/icoll-imx233.c
new file mode 100644
index 0000000000..4e0d525da3
--- /dev/null
+++ b/firmware/target/arm/imx233/icoll-imx233.c
@@ -0,0 +1,177 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2012 by amaury Pouly
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22#include "icoll-imx233.h"
23#include "rtc-imx233.h"
24#include "string.h"
25
26#define default_interrupt(name) \
27 extern __attribute__((weak, alias("UIRQ"))) void name(void)
28
29static void UIRQ (void) __attribute__((interrupt ("IRQ")));
30void irq_handler(void) __attribute__((interrupt("IRQ")));
31void fiq_handler(void) __attribute__((interrupt("FIQ")));
32
33default_interrupt(INT_USB_CTRL);
34default_interrupt(INT_TIMER0);
35default_interrupt(INT_TIMER1);
36default_interrupt(INT_TIMER2);
37default_interrupt(INT_TIMER3);
38default_interrupt(INT_LCDIF_DMA);
39default_interrupt(INT_LCDIF_ERROR);
40default_interrupt(INT_SSP1_DMA);
41default_interrupt(INT_SSP1_ERROR);
42default_interrupt(INT_SSP2_DMA);
43default_interrupt(INT_SSP2_ERROR);
44default_interrupt(INT_I2C_DMA);
45default_interrupt(INT_I2C_ERROR);
46default_interrupt(INT_GPIO0);
47default_interrupt(INT_GPIO1);
48default_interrupt(INT_GPIO2);
49default_interrupt(INT_VDD5V);
50default_interrupt(INT_LRADC_CH0);
51default_interrupt(INT_LRADC_CH1);
52default_interrupt(INT_LRADC_CH2);
53default_interrupt(INT_LRADC_CH3);
54default_interrupt(INT_LRADC_CH4);
55default_interrupt(INT_LRADC_CH5);
56default_interrupt(INT_LRADC_CH6);
57default_interrupt(INT_LRADC_CH7);
58default_interrupt(INT_DAC_DMA);
59default_interrupt(INT_DAC_ERROR);
60default_interrupt(INT_ADC_DMA);
61default_interrupt(INT_ADC_ERROR);
62default_interrupt(INT_DCP);
63default_interrupt(INT_TOUCH_DETECT);
64
65void INT_RTC_1MSEC(void);
66
67typedef void (*isr_t)(void);
68
69static isr_t isr_table[INT_SRC_NR_SOURCES] =
70{
71 [INT_SRC_USB_CTRL] = INT_USB_CTRL,
72 [INT_SRC_TIMER(0)] = INT_TIMER0,
73 [INT_SRC_TIMER(1)] = INT_TIMER1,
74 [INT_SRC_TIMER(2)] = INT_TIMER2,
75 [INT_SRC_TIMER(3)] = INT_TIMER3,
76 [INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA,
77 [INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR,
78 [INT_SRC_SSP1_DMA] = INT_SSP1_DMA,
79 [INT_SRC_SSP1_ERROR] = INT_SSP1_ERROR,
80 [INT_SRC_SSP2_DMA] = INT_SSP2_DMA,
81 [INT_SRC_SSP2_ERROR] = INT_SSP2_ERROR,
82 [INT_SRC_I2C_DMA] = INT_I2C_DMA,
83 [INT_SRC_I2C_ERROR] = INT_I2C_ERROR,
84 [INT_SRC_GPIO0] = INT_GPIO0,
85 [INT_SRC_GPIO1] = INT_GPIO1,
86 [INT_SRC_GPIO2] = INT_GPIO2,
87 [INT_SRC_VDD5V] = INT_VDD5V,
88 [INT_SRC_LRADC_CHx(0)] = INT_LRADC_CH0,
89 [INT_SRC_LRADC_CHx(1)] = INT_LRADC_CH1,
90 [INT_SRC_LRADC_CHx(2)] = INT_LRADC_CH2,
91 [INT_SRC_LRADC_CHx(3)] = INT_LRADC_CH3,
92 [INT_SRC_LRADC_CHx(4)] = INT_LRADC_CH4,
93 [INT_SRC_LRADC_CHx(5)] = INT_LRADC_CH5,
94 [INT_SRC_LRADC_CHx(6)] = INT_LRADC_CH6,
95 [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7,
96 [INT_SRC_DAC_DMA] = INT_DAC_DMA,
97 [INT_SRC_DAC_ERROR] = INT_DAC_ERROR,
98 [INT_SRC_ADC_DMA] = INT_ADC_DMA,
99 [INT_SRC_ADC_ERROR] = INT_ADC_ERROR,
100 [INT_SRC_DCP] = INT_DCP,
101 [INT_SRC_TOUCH_DETECT] = INT_TOUCH_DETECT,
102 [INT_SRC_RTC_1MSEC] = INT_RTC_1MSEC,
103};
104
105#define IRQ_STORM_DELAY 1000 /* ms */
106#define IRQ_STORM_THRESHOLD 100000 /* allows irq / delay */
107
108static uint32_t irq_count_old[INT_SRC_NR_SOURCES];
109static uint32_t irq_count[INT_SRC_NR_SOURCES];
110
111struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src)
112{
113 struct imx233_icoll_irq_info_t info;
114 info.enabled = !!(HW_ICOLL_INTERRUPT(src) & HW_ICOLL_INTERRUPT__ENABLE);
115 info.freq = irq_count_old[src];
116 return info;
117}
118
119void INT_RTC_1MSEC(void)
120{
121 static unsigned counter = 0;
122 if(counter++ >= IRQ_STORM_DELAY)
123 {
124 counter = 0;
125 memcpy(irq_count_old, irq_count, sizeof(irq_count));
126 memset(irq_count, 0, sizeof(irq_count));
127 }
128 imx233_rtc_clear_msec_irq();
129}
130
131static void UIRQ(void)
132{
133 panicf("Unhandled IRQ %02X",
134 (unsigned int)(HW_ICOLL_VECTOR - (uint32_t)isr_table) / 4);
135}
136
137void irq_handler(void)
138{
139 HW_ICOLL_VECTOR = HW_ICOLL_VECTOR; /* notify icoll that we entered ISR */
140 int irq_nr = (HW_ICOLL_VECTOR - HW_ICOLL_VBASE) / 4;
141 if(irq_count[irq_nr]++ > IRQ_STORM_THRESHOLD)
142 panicf("IRQ %d: storm detected", irq_nr);
143 (*(isr_t *)HW_ICOLL_VECTOR)();
144 /* acknowledge completion of IRQ (all use the same priority 0) */
145 HW_ICOLL_LEVELACK = HW_ICOLL_LEVELACK__LEVEL0;
146}
147
148void fiq_handler(void)
149{
150}
151
152void imx233_icoll_enable_interrupt(int src, bool enable)
153{
154 if(enable)
155 __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
156 else
157 __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
158}
159
160void imx233_icoll_init(void)
161{
162 imx233_reset_block(&HW_ICOLL_CTRL);
163 /* disable all interrupts */
164 for(int i = 0; i < INT_SRC_NR_SOURCES; i++)
165 {
166 /* priority = 0, disable, disable fiq */
167 HW_ICOLL_INTERRUPT(i) = 0;
168 }
169 /* setup vbase as isr_table */
170 HW_ICOLL_VBASE = (uint32_t)&isr_table;
171 /* enable final irq bit */
172 __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE;
173
174 imx233_rtc_enable_msec_irq(true);
175 imx233_icoll_enable_interrupt(INT_SRC_RTC_1MSEC, true);
176}
177
diff --git a/firmware/target/arm/imx233/icoll-imx233.h b/firmware/target/arm/imx233/icoll-imx233.h
new file mode 100644
index 0000000000..d1bf8a18aa
--- /dev/null
+++ b/firmware/target/arm/imx233/icoll-imx233.h
@@ -0,0 +1,81 @@
1/***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2012 by Amaury Pouly
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21#ifndef ICOLL_IMX233_H
22#define ICOLL_IMX233_H
23
24#include "config.h"
25#include "system.h"
26
27/* Interrupt collector */
28#define HW_ICOLL_BASE 0x80000000
29
30#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
31
32#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
33#define HW_ICOLL_LEVELACK__LEVEL0 0x1
34
35#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
36#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
37#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
38
39#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
40#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
41#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
42#define HW_ICOLL_INTERRUPT__ENABLE 0x4
43#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
44#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
45
46#define INT_SRC_SSP2_ERROR 2
47#define INT_SRC_VDD5V 3
48#define INT_SRC_DAC_DMA 5
49#define INT_SRC_DAC_ERROR 6
50#define INT_SRC_ADC_DMA 7
51#define INT_SRC_ADC_ERROR 8
52#define INT_SRC_USB_CTRL 11
53#define INT_SRC_SSP1_DMA 14
54#define INT_SRC_SSP1_ERROR 15
55#define INT_SRC_GPIO0 16
56#define INT_SRC_GPIO1 17
57#define INT_SRC_GPIO2 18
58#define INT_SRC_GPIO(i) (INT_SRC_GPIO0 + (i))
59#define INT_SRC_SSP2_DMA 20
60#define INT_SRC_I2C_DMA 26
61#define INT_SRC_I2C_ERROR 27
62#define INT_SRC_TIMER(nr) (28 + (nr))
63#define INT_SRC_TOUCH_DETECT 36
64#define INT_SRC_LRADC_CHx(x) (37 + (x))
65#define INT_SRC_LCDIF_DMA 45
66#define INT_SRC_LCDIF_ERROR 46
67#define INT_SRC_RTC_1MSEC 48
68#define INT_SRC_DCP 54
69#define INT_SRC_NR_SOURCES 66
70
71struct imx233_icoll_irq_info_t
72{
73 bool enabled;
74 unsigned freq;
75};
76
77void imx233_icoll_init(void);
78void imx233_icoll_enable_interrupt(int src, bool enable);
79struct imx233_icoll_irq_info_t imx233_icoll_get_irq_info(int src);
80
81#endif /* ICOLL_IMX233_H */
diff --git a/firmware/target/arm/imx233/pcm-imx233.c b/firmware/target/arm/imx233/pcm-imx233.c
index c4c512eed6..e94260e457 100644
--- a/firmware/target/arm/imx233/pcm-imx233.c
+++ b/firmware/target/arm/imx233/pcm-imx233.c
@@ -103,8 +103,8 @@ void pcm_play_dma_init(void)
103void pcm_play_dma_postinit(void) 103void pcm_play_dma_postinit(void)
104{ 104{
105 audiohw_postinit(); 105 audiohw_postinit();
106 imx233_enable_interrupt(INT_SRC_DAC_DMA, true); 106 imx233_icoll_enable_interrupt(INT_SRC_DAC_DMA, true);
107 imx233_enable_interrupt(INT_SRC_DAC_ERROR, true); 107 imx233_icoll_enable_interrupt(INT_SRC_DAC_ERROR, true);
108 imx233_dma_enable_channel_interrupt(APB_AUDIO_DAC, true); 108 imx233_dma_enable_channel_interrupt(APB_AUDIO_DAC, true);
109} 109}
110 110
diff --git a/firmware/target/arm/imx233/pinctrl-imx233.c b/firmware/target/arm/imx233/pinctrl-imx233.c
index be2d8b2262..d667e8d25c 100644
--- a/firmware/target/arm/imx233/pinctrl-imx233.c
+++ b/firmware/target/arm/imx233/pinctrl-imx233.c
@@ -111,6 +111,6 @@ void imx233_setup_pin_irq(int bank, int pin, bool enable_int,
111 __REG_CLR(HW_PINCTRL_IRQPOL(bank)) = 1 << pin; 111 __REG_CLR(HW_PINCTRL_IRQPOL(bank)) = 1 << pin;
112 __REG_SET(HW_PINCTRL_PIN2IRQ(bank)) = 1 << pin; 112 __REG_SET(HW_PINCTRL_PIN2IRQ(bank)) = 1 << pin;
113 __REG_SET(HW_PINCTRL_IRQEN(bank)) = 1 << pin; 113 __REG_SET(HW_PINCTRL_IRQEN(bank)) = 1 << pin;
114 imx233_enable_interrupt(INT_SRC_GPIO(bank), true); 114 imx233_icoll_enable_interrupt(INT_SRC_GPIO(bank), true);
115 } 115 }
116} 116}
diff --git a/firmware/target/arm/imx233/power-imx233.c b/firmware/target/arm/imx233/power-imx233.c
index be12207793..6ba08ae394 100644
--- a/firmware/target/arm/imx233/power-imx233.c
+++ b/firmware/target/arm/imx233/power-imx233.c
@@ -96,7 +96,7 @@ void power_init(void)
96 else 96 else
97 __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID; 97 __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__POLARITY_VBUSVALID;
98 __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID; 98 __REG_SET(HW_POWER_CTRL) = HW_POWER_CTRL__ENIRQ_VBUS_VALID;
99 imx233_enable_interrupt(INT_SRC_VDD5V, true); 99 imx233_icoll_enable_interrupt(INT_SRC_VDD5V, true);
100 /* setup linear regulator offsets to 25 mV below to prevent contention between 100 /* setup linear regulator offsets to 25 mV below to prevent contention between
101 * linear regulators and DCDC */ 101 * linear regulators and DCDC */
102 __FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2); 102 __FIELD_SET(HW_POWER_VDDDCTRL, LINREG_OFFSET, 2);
diff --git a/firmware/target/arm/imx233/ssp-imx233.c b/firmware/target/arm/imx233/ssp-imx233.c
index bdbde9ec93..1dd2d767ba 100644
--- a/firmware/target/arm/imx233/ssp-imx233.c
+++ b/firmware/target/arm/imx233/ssp-imx233.c
@@ -245,7 +245,7 @@ enum imx233_ssp_error_t imx233_ssp_sd_mmc_transfer(int ssp, uint8_t cmd,
245{ 245{
246 mutex_lock(&ssp_mutex[ssp - 1]); 246 mutex_lock(&ssp_mutex[ssp - 1]);
247 /* Enable all interrupts */ 247 /* Enable all interrupts */
248 imx233_enable_interrupt(INT_SRC_SSP_DMA(ssp), true); 248 imx233_icoll_enable_interrupt(INT_SRC_SSP_DMA(ssp), true);
249 imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true); 249 imx233_dma_enable_channel_interrupt(APB_SSP(ssp), true);
250 250
251 unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]); 251 unsigned xfer_size = block_count * (1 << ssp_log_block_size[ssp - 1]);
diff --git a/firmware/target/arm/imx233/system-imx233.c b/firmware/target/arm/imx233/system-imx233.c
index 51eb099709..a06ecab9f5 100644
--- a/firmware/target/arm/imx233/system-imx233.c
+++ b/firmware/target/arm/imx233/system-imx233.c
@@ -31,6 +31,7 @@
31#include "ssp-imx233.h" 31#include "ssp-imx233.h"
32#include "i2c-imx233.h" 32#include "i2c-imx233.h"
33#include "dcp-imx233.h" 33#include "dcp-imx233.h"
34#include "icoll-imx233.h"
34#include "lradc-imx233.h" 35#include "lradc-imx233.h"
35#include "rtc-imx233.h" 36#include "rtc-imx233.h"
36#include "lcd.h" 37#include "lcd.h"
@@ -38,98 +39,6 @@
38#include "button.h" 39#include "button.h"
39#include "fmradio_i2c.h" 40#include "fmradio_i2c.h"
40 41
41#define default_interrupt(name) \
42 extern __attribute__((weak, alias("UIRQ"))) void name(void)
43
44static void UIRQ (void) __attribute__((interrupt ("IRQ")));
45void irq_handler(void) __attribute__((interrupt("IRQ")));
46void fiq_handler(void) __attribute__((interrupt("FIQ")));
47
48default_interrupt(INT_USB_CTRL);
49default_interrupt(INT_TIMER0);
50default_interrupt(INT_TIMER1);
51default_interrupt(INT_TIMER2);
52default_interrupt(INT_TIMER3);
53default_interrupt(INT_LCDIF_DMA);
54default_interrupt(INT_LCDIF_ERROR);
55default_interrupt(INT_SSP1_DMA);
56default_interrupt(INT_SSP1_ERROR);
57default_interrupt(INT_SSP2_DMA);
58default_interrupt(INT_SSP2_ERROR);
59default_interrupt(INT_I2C_DMA);
60default_interrupt(INT_I2C_ERROR);
61default_interrupt(INT_GPIO0);
62default_interrupt(INT_GPIO1);
63default_interrupt(INT_GPIO2);
64default_interrupt(INT_VDD5V);
65default_interrupt(INT_LRADC_CH0);
66default_interrupt(INT_LRADC_CH1);
67default_interrupt(INT_LRADC_CH2);
68default_interrupt(INT_LRADC_CH3);
69default_interrupt(INT_LRADC_CH4);
70default_interrupt(INT_LRADC_CH5);
71default_interrupt(INT_LRADC_CH6);
72default_interrupt(INT_LRADC_CH7);
73default_interrupt(INT_DAC_DMA);
74default_interrupt(INT_DAC_ERROR);
75default_interrupt(INT_ADC_DMA);
76default_interrupt(INT_ADC_ERROR);
77default_interrupt(INT_DCP);
78
79typedef void (*isr_t)(void);
80
81static isr_t isr_table[INT_SRC_NR_SOURCES] =
82{
83 [INT_SRC_USB_CTRL] = INT_USB_CTRL,
84 [INT_SRC_TIMER(0)] = INT_TIMER0,
85 [INT_SRC_TIMER(1)] = INT_TIMER1,
86 [INT_SRC_TIMER(2)] = INT_TIMER2,
87 [INT_SRC_TIMER(3)] = INT_TIMER3,
88 [INT_SRC_LCDIF_DMA] = INT_LCDIF_DMA,
89 [INT_SRC_LCDIF_ERROR] = INT_LCDIF_ERROR,
90 [INT_SRC_SSP1_DMA] = INT_SSP1_DMA,
91 [INT_SRC_SSP1_ERROR] = INT_SSP1_ERROR,
92 [INT_SRC_SSP2_DMA] = INT_SSP2_DMA,
93 [INT_SRC_SSP2_ERROR] = INT_SSP2_ERROR,
94 [INT_SRC_I2C_DMA] = INT_I2C_DMA,
95 [INT_SRC_I2C_ERROR] = INT_I2C_ERROR,
96 [INT_SRC_GPIO0] = INT_GPIO0,
97 [INT_SRC_GPIO1] = INT_GPIO1,
98 [INT_SRC_GPIO2] = INT_GPIO2,
99 [INT_SRC_VDD5V] = INT_VDD5V,
100 [INT_SRC_LRADC_CHx(0)] = INT_LRADC_CH0,
101 [INT_SRC_LRADC_CHx(1)] = INT_LRADC_CH1,
102 [INT_SRC_LRADC_CHx(2)] = INT_LRADC_CH2,
103 [INT_SRC_LRADC_CHx(3)] = INT_LRADC_CH3,
104 [INT_SRC_LRADC_CHx(4)] = INT_LRADC_CH4,
105 [INT_SRC_LRADC_CHx(5)] = INT_LRADC_CH5,
106 [INT_SRC_LRADC_CHx(6)] = INT_LRADC_CH6,
107 [INT_SRC_LRADC_CHx(7)] = INT_LRADC_CH7,
108 [INT_SRC_DAC_DMA] = INT_DAC_DMA,
109 [INT_SRC_DAC_ERROR] = INT_DAC_ERROR,
110 [INT_SRC_ADC_DMA] = INT_ADC_DMA,
111 [INT_SRC_ADC_ERROR] = INT_ADC_ERROR,
112 [INT_SRC_DCP] = INT_DCP,
113};
114
115static void UIRQ(void)
116{
117 panicf("Unhandled IRQ %02X",
118 (unsigned int)(HW_ICOLL_VECTOR - (uint32_t)isr_table) / 4);
119}
120
121void irq_handler(void)
122{
123 HW_ICOLL_VECTOR = HW_ICOLL_VECTOR; /* notify icoll that we entered ISR */
124 (*(isr_t *)HW_ICOLL_VECTOR)();
125 /* acknowledge completion of IRQ (all use the same priority 0) */
126 HW_ICOLL_LEVELACK = HW_ICOLL_LEVELACK__LEVEL0;
127}
128
129void fiq_handler(void)
130{
131}
132
133void imx233_chip_reset(void) 42void imx233_chip_reset(void)
134{ 43{
135 HW_CLKCTRL_RESET = HW_CLKCTRL_RESET_CHIP; 44 HW_CLKCTRL_RESET = HW_CLKCTRL_RESET_CHIP;
@@ -164,22 +73,6 @@ int system_memory_guard(int newmode)
164 return 0; 73 return 0;
165} 74}
166 75
167void imx233_enable_interrupt(int src, bool enable)
168{
169 if(enable)
170 __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
171 else
172 __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__ENABLE;
173}
174
175void imx233_softirq(int src, bool enable)
176{
177 if(enable)
178 __REG_SET(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ;
179 else
180 __REG_CLR(HW_ICOLL_INTERRUPT(src)) = HW_ICOLL_INTERRUPT__SOFTIRQ;
181}
182
183static void set_page_tables(void) 76static void set_page_tables(void)
184{ 77{
185 /* map every memory region to itself */ 78 /* map every memory region to itself */
@@ -199,19 +92,8 @@ void memory_init(void)
199 92
200void system_init(void) 93void system_init(void)
201{ 94{
202 imx233_reset_block(&HW_ICOLL_CTRL);
203 /* disable all interrupts */
204 for(int i = 0; i < INT_SRC_NR_SOURCES; i++)
205 {
206 /* priority = 0, disable, disable fiq */
207 HW_ICOLL_INTERRUPT(i) = 0;
208 }
209 /* setup vbase as isr_table */
210 HW_ICOLL_VBASE = (uint32_t)&isr_table;
211 /* enable final irq bit */
212 __REG_SET(HW_ICOLL_CTRL) = HW_ICOLL_CTRL__IRQ_FINAL_ENABLE;
213
214 imx233_rtc_init(); 95 imx233_rtc_init();
96 imx233_icoll_init();
215 imx233_pinctrl_init(); 97 imx233_pinctrl_init();
216 imx233_timrot_init(); 98 imx233_timrot_init();
217 imx233_dma_init(); 99 imx233_dma_init();
diff --git a/firmware/target/arm/imx233/system-target.h b/firmware/target/arm/imx233/system-target.h
index d9a19efa8f..2e850e830d 100644
--- a/firmware/target/arm/imx233/system-target.h
+++ b/firmware/target/arm/imx233/system-target.h
@@ -25,6 +25,7 @@
25#include "mmu-arm.h" 25#include "mmu-arm.h"
26#include "panic.h" 26#include "panic.h"
27#include "clkctrl-imx233.h" 27#include "clkctrl-imx233.h"
28#include "icoll-imx233.h"
28#include "clock-target.h" /* CPUFREQ_* are defined here */ 29#include "clock-target.h" /* CPUFREQ_* are defined here */
29 30
30/* Digital control */ 31/* Digital control */
@@ -43,48 +44,6 @@
43 44
44#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30)) 45#define HW_USBPHY_CTRL (*(volatile uint32_t *)(HW_USBPHY_BASE + 0x30))
45 46
46/* Interrupt collector */
47#define HW_ICOLL_BASE 0x80000000
48
49#define HW_ICOLL_VECTOR (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x0))
50
51#define HW_ICOLL_LEVELACK (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x10))
52#define HW_ICOLL_LEVELACK__LEVEL0 0x1
53
54#define HW_ICOLL_CTRL (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x20))
55#define HW_ICOLL_CTRL__IRQ_FINAL_ENABLE (1 << 16)
56#define HW_ICOLL_CTRL__ARM_RSE_MODE (1 << 18)
57
58#define HW_ICOLL_VBASE (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x40))
59#define HW_ICOLL_INTERRUPT(i) (*(volatile uint32_t *)(HW_ICOLL_BASE + 0x120 + (i) * 0x10))
60#define HW_ICOLL_INTERRUPT__PRIORITY_BM 0x3
61#define HW_ICOLL_INTERRUPT__ENABLE 0x4
62#define HW_ICOLL_INTERRUPT__SOFTIRQ 0x8
63#define HW_ICOLL_INTERRUPT__ENFIQ 0x10
64
65#define INT_SRC_SSP2_ERROR 2
66#define INT_SRC_VDD5V 3
67#define INT_SRC_DAC_DMA 5
68#define INT_SRC_DAC_ERROR 6
69#define INT_SRC_ADC_DMA 7
70#define INT_SRC_ADC_ERROR 8
71#define INT_SRC_USB_CTRL 11
72#define INT_SRC_SSP1_DMA 14
73#define INT_SRC_SSP1_ERROR 15
74#define INT_SRC_GPIO0 16
75#define INT_SRC_GPIO1 17
76#define INT_SRC_GPIO2 18
77#define INT_SRC_GPIO(i) (INT_SRC_GPIO0 + (i))
78#define INT_SRC_SSP2_DMA 20
79#define INT_SRC_I2C_DMA 26
80#define INT_SRC_I2C_ERROR 27
81#define INT_SRC_TIMER(nr) (28 + (nr))
82#define INT_SRC_LRADC_CHx(x) (37 + (x))
83#define INT_SRC_LCDIF_DMA 45
84#define INT_SRC_LCDIF_ERROR 46
85#define INT_SRC_DCP 54
86#define INT_SRC_NR_SOURCES 66
87
88/** 47/**
89 * Absolute maximum CPU speed: 454.74 MHz 48 * Absolute maximum CPU speed: 454.74 MHz
90 * Intermediate CPU speeds: 392.73 MHz, 360MHz, 261.82 MHz, 64 MHz 49 * Intermediate CPU speeds: 392.73 MHz, 360MHz, 261.82 MHz, 64 MHz
@@ -101,8 +60,6 @@
101#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz 60#define CPUFREQ_MAX IMX233_CPUFREQ_454_MHz
102#define CPUFREQ_SLEEP IMX233_CPUFREQ_454_MHz 61#define CPUFREQ_SLEEP IMX233_CPUFREQ_454_MHz
103 62
104void imx233_enable_interrupt(int src, bool enable);
105void imx233_softirq(int src, bool enable);
106void udelay(unsigned us); 63void udelay(unsigned us);
107bool imx233_us_elapsed(uint32_t ref, unsigned us_delay); 64bool imx233_us_elapsed(uint32_t ref, unsigned us_delay);
108void imx233_reset_block(volatile uint32_t *block_reg); 65void imx233_reset_block(volatile uint32_t *block_reg);
diff --git a/firmware/target/arm/imx233/timrot-imx233.c b/firmware/target/arm/imx233/timrot-imx233.c
index 24ed0096ab..327b1d16b1 100644
--- a/firmware/target/arm/imx233/timrot-imx233.c
+++ b/firmware/target/arm/imx233/timrot-imx233.c
@@ -58,13 +58,13 @@ void imx233_setup_timer(unsigned timer_nr, bool reload, unsigned count,
58 if(fn != NULL) 58 if(fn != NULL)
59 { 59 {
60 /* enable interrupt */ 60 /* enable interrupt */
61 imx233_enable_interrupt(INT_SRC_TIMER(timer_nr), true); 61 imx233_icoll_enable_interrupt(INT_SRC_TIMER(timer_nr), true);
62 /* clear irq bit and enable */ 62 /* clear irq bit and enable */
63 __REG_CLR(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__IRQ; 63 __REG_CLR(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__IRQ;
64 __REG_SET(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__IRQ_EN; 64 __REG_SET(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__IRQ_EN;
65 } 65 }
66 else 66 else
67 imx233_enable_interrupt(INT_SRC_TIMER(timer_nr), false); 67 imx233_icoll_enable_interrupt(INT_SRC_TIMER(timer_nr), false);
68 /* finally update */ 68 /* finally update */
69 __REG_SET(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__UPDATE; 69 __REG_SET(HW_TIMROT_TIMCTRL(timer_nr)) = HW_TIMROT_TIMCTRL__UPDATE;
70 70
diff --git a/firmware/target/arm/imx233/usb-imx233.c b/firmware/target/arm/imx233/usb-imx233.c
index 304018b09b..409dcd340d 100644
--- a/firmware/target/arm/imx233/usb-imx233.c
+++ b/firmware/target/arm/imx233/usb-imx233.c
@@ -47,7 +47,7 @@ void usb_attach(void)
47 47
48void usb_drv_int_enable(bool enable) 48void usb_drv_int_enable(bool enable)
49{ 49{
50 imx233_enable_interrupt(INT_SRC_USB_CTRL, enable); 50 imx233_icoll_enable_interrupt(INT_SRC_USB_CTRL, enable);
51} 51}
52 52
53void INT_USB_CTRL(void) 53void INT_USB_CTRL(void)