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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-29 00:26:22 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-29 00:29:25 -0400 |
commit | 5e335f5c33cb9e72c6615c503a876e57b8176dab (patch) | |
tree | d3a1c16d461530a32c04b1977b08b3f693499d5b /firmware/target | |
parent | fc7eb3b2a399104f72699a6a3a795106250058a8 (diff) | |
download | rockbox-5e335f5c33cb9e72c6615c503a876e57b8176dab.tar.gz rockbox-5e335f5c33cb9e72c6615c503a876e57b8176dab.zip |
jz4760: do the MSC (ie SD) clocking setup when we change PLL0
Change-Id: Ia17b1d7069af507c3f029bcaed0f65e7e97df275
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 34 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 10 |
2 files changed, 13 insertions, 31 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c index 881c83066e..8da1313cf8 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |||
@@ -689,12 +689,18 @@ void DMA_CALLBACK(DMA_SD_TX_CHANNEL1)(void) | |||
689 | #endif /* SD_DMA_INTERRUPT */ | 689 | #endif /* SD_DMA_INTERRUPT */ |
690 | #endif /* SD_DMA_ENABLE */ | 690 | #endif /* SD_DMA_ENABLE */ |
691 | 691 | ||
692 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | ||
693 | #define cpu_frequency __cpm_get_pllout2() | ||
694 | #endif | ||
695 | |||
692 | static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | 696 | static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) |
693 | { | 697 | { |
694 | unsigned int clkrt; | 698 | unsigned int clkrt = 0; |
695 | unsigned int clk_src = sd2_0[drive] ? SD_CLOCK_HIGH : SD_CLOCK_FAST; | 699 | unsigned int clk_src = cpu_frequency / __cpm_get_mscdiv(); /* MSC_CLK */ |
700 | |||
701 | if (!sd2_0[drive] && rate > SD_CLOCK_FAST) | ||
702 | rate = SD_CLOCK_FAST; | ||
696 | 703 | ||
697 | clkrt = 0; | ||
698 | while (rate < clk_src) | 704 | while (rate < clk_src) |
699 | { | 705 | { |
700 | clkrt++; | 706 | clkrt++; |
@@ -703,33 +709,11 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | |||
703 | return clkrt; | 709 | return clkrt; |
704 | } | 710 | } |
705 | 711 | ||
706 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ | ||
707 | #define cpu_frequency __cpm_get_pllout2() | ||
708 | #endif | ||
709 | |||
710 | void cpm_select_msc_clk(void) | ||
711 | { | ||
712 | unsigned int div = cpu_frequency / SD_CLOCK_FAST; | ||
713 | |||
714 | if (div == 0) | ||
715 | div = 1; | ||
716 | |||
717 | if (div == __cpm_get_mscdiv()) | ||
718 | return; | ||
719 | |||
720 | REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); | ||
721 | DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); | ||
722 | __cpm_enable_pll_change(); | ||
723 | } | ||
724 | |||
725 | /* Set the MMC clock frequency */ | 712 | /* Set the MMC clock frequency */ |
726 | static void jz_sd_set_clock(const int drive, unsigned int rate) | 713 | static void jz_sd_set_clock(const int drive, unsigned int rate) |
727 | { | 714 | { |
728 | int clkrt; | 715 | int clkrt; |
729 | 716 | ||
730 | /* select clock source from CPM */ | ||
731 | cpm_select_msc_clk(); | ||
732 | |||
733 | clkrt = jz_sd_calc_clkrt(drive, rate); | 717 | clkrt = jz_sd_calc_clkrt(drive, rate); |
734 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; | 718 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; |
735 | 719 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index d94bea3f00..eab3ef64e6 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -491,12 +491,14 @@ static void pll0_init(unsigned int freq) | |||
491 | | CPPCR0_PLLEN; /* enable PLL */ | 491 | | CPPCR0_PLLEN; /* enable PLL */ |
492 | 492 | ||
493 | /* | 493 | /* |
494 | * Init USB Host clock, pllout2 must be n*48MHz | 494 | * Init USB Host clock, PLL0 must be multiple of 48MHz! |
495 | * For JZ4760b UHC - River. | ||
496 | */ | 495 | */ |
497 | usbdiv = (cfcr & CPCCR_PCS) ? freq : (freq / 2); | 496 | usbdiv = (cfcr & CPCCR_PCS) ? freq : (freq / 2); |
498 | REG_CPM_UHCCDR = usbdiv / 48000000 - 1; | 497 | REG_CPM_UHCCDR = usbdiv / 48000000 - 1; |
499 | 498 | ||
499 | /* Init MSC clock; shoot for 48MHz base clock. */ | ||
500 | REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1); | ||
501 | |||
500 | /* init PLL */ | 502 | /* init PLL */ |
501 | REG_CPM_CPCCR = cfcr; | 503 | REG_CPM_CPCCR = cfcr; |
502 | REG_CPM_CPPCR0 = plcr1; | 504 | REG_CPM_CPPCR0 = plcr1; |
@@ -756,10 +758,7 @@ int system_memory_guard(int newmode) | |||
756 | return 0; | 758 | return 0; |
757 | } | 759 | } |
758 | 760 | ||
759 | |||
760 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 761 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
761 | void cpm_select_msc_clk(void); | ||
762 | |||
763 | void set_cpu_frequency(long frequency) | 762 | void set_cpu_frequency(long frequency) |
764 | { | 763 | { |
765 | if (frequency == cpu_frequency) | 764 | if (frequency == cpu_frequency) |
@@ -771,6 +770,5 @@ void set_cpu_frequency(long frequency) | |||
771 | 770 | ||
772 | pll0_init(frequency); | 771 | pll0_init(frequency); |
773 | cpu_frequency = __cpm_get_pllout2(); | 772 | cpu_frequency = __cpm_get_pllout2(); |
774 | cpm_select_msc_clk(); | ||
775 | } | 773 | } |
776 | #endif | 774 | #endif |