diff options
author | Marcin Bukat <marcin.bukat@gmail.com> | 2012-03-22 23:45:27 +0100 |
---|---|---|
committer | Marcin Bukat <marcin.bukat@gmail.com> | 2012-03-22 23:48:31 +0100 |
commit | 5513c6db56e6de82561bbf90f3f0af12045be6d5 (patch) | |
tree | 3a26f9d2a75ec37b4b95d840a86c07cf143790c7 /firmware/target | |
parent | 2e03c2a8b346e466ff877ddfba7204a255895280 (diff) | |
download | rockbox-5513c6db56e6de82561bbf90f3f0af12045be6d5.tar.gz rockbox-5513c6db56e6de82561bbf90f3f0af12045be6d5.zip |
rk27xx: implement system_init()
For now it contains explicit SDRAM setup, cutting clock for unused
modules and turning off unused PLLs. This improves slightly mem
throughput as well as saves quite a bit of power.
Change-Id: I19a2827ac90a6868856c676fbe1e051c42f0d608
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/rk27xx/system-rk27xx.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/firmware/target/arm/rk27xx/system-rk27xx.c b/firmware/target/arm/rk27xx/system-rk27xx.c index ac423955d6..0e7fca4c06 100644 --- a/firmware/target/arm/rk27xx/system-rk27xx.c +++ b/firmware/target/arm/rk27xx/system-rk27xx.c | |||
@@ -117,6 +117,34 @@ void fiq_dummy(void) | |||
117 | 117 | ||
118 | void system_init(void) | 118 | void system_init(void) |
119 | { | 119 | { |
120 | /* SDRAM tweaks */ | ||
121 | MCSDR_MODE = (2<<4)|3; /* CAS=2, burst=8 */ | ||
122 | MCSDR_T_REF = (125*100) >> 3; /* 125/8 = 15.625 autorefresh interval */ | ||
123 | MCSDR_T_RFC = (64*100) / 1000; /* autorefresh period */ | ||
124 | MCSDR_T_RP = 1; /* precharge period */ | ||
125 | MCSDR_T_RCD = 1; /* active to RD/WR delay */ | ||
126 | |||
127 | /* turn off clock for unused modules */ | ||
128 | SCU_CLKCFG |= (1<<31) | /* WDT pclk */ | ||
129 | (1<<30) | /* RTC pclk */ | ||
130 | (1<<26) | /* HS_ADC clock */ | ||
131 | (1<<25) | /* HS_ADC HCLK */ | ||
132 | (1<<21) | /* SPI clock */ | ||
133 | (1<<19) | /* UART1 clock */ | ||
134 | (1<<18) | /* UART0 clock */ | ||
135 | (1<<15) | /* VIP clock */ | ||
136 | (1<<14) | /* VIP HCLK */ | ||
137 | (1<<13) | /* LCDC clock */ | ||
138 | (1<<9) | /* NAND HCLK */ | ||
139 | (1<<5) | /* USB host HCLK */ | ||
140 | (1<<1) | /* DSP clock */ | ||
141 | (1<<0); /* OTP clock (dunno what it is */ | ||
142 | |||
143 | /* turn off DSP pll */ | ||
144 | SCU_PLLCON2 |= (1<<22); | ||
145 | |||
146 | /* turn off codec pll */ | ||
147 | SCU_PLLCON3 |= (1<<22); | ||
120 | return; | 148 | return; |
121 | } | 149 | } |
122 | 150 | ||
@@ -124,6 +152,7 @@ void system_init(void) | |||
124 | void system_reboot(void) | 152 | void system_reboot(void) |
125 | { | 153 | { |
126 | /* use Watchdog to reset */ | 154 | /* use Watchdog to reset */ |
155 | SCU_CLKCFG &= ~(1<<31); | ||
127 | WDTLR = 1; | 156 | WDTLR = 1; |
128 | WDTCON = (1<<4) | (1<<3); | 157 | WDTCON = (1<<4) | (1<<3); |
129 | 158 | ||