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author | Cástor Muñoz <cmvidal@gmail.com> | 2016-06-10 00:34:22 +0200 |
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committer | Cástor Muñoz <cmvidal@gmail.com> | 2016-06-10 00:34:23 +0200 |
commit | 489044d1ca9314c79a50768565f4c36a6c4cfc06 (patch) | |
tree | 3630ecd48af3c12ad58640bd9e70340fd5b11946 /firmware/target | |
parent | 9a6700d52e8dfb2e93623e7143204ae34f798bbf (diff) | |
download | rockbox-489044d1ca9314c79a50768565f4c36a6c4cfc06.tar.gz rockbox-489044d1ca9314c79a50768565f4c36a6c4cfc06.zip |
iPod Nano2G: clear external interrupts at startup
Fixes some ROLO issues after commit 9a4cd2e. Note that other ROLO
issues still persist.
Change-Id: I8e0c60519902013694c5a473dcb9fc62a6ff079c
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/s5l8700/crt0.S | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/firmware/target/arm/s5l8700/crt0.S b/firmware/target/arm/s5l8700/crt0.S index 93bfa8f06c..b13d89b7e9 100644 --- a/firmware/target/arm/s5l8700/crt0.S +++ b/firmware/target/arm/s5l8700/crt0.S | |||
@@ -82,12 +82,24 @@ newstart2: | |||
82 | 82 | ||
83 | mov r0, #0 | 83 | mov r0, #0 |
84 | mov r1, #0x39c00000 | 84 | mov r1, #0x39c00000 |
85 | str r0, [r1,#0x08] // mask all interrupts | 85 | str r0, [r1,#0x08] /* mask all interrupts */ |
86 | str r0, [r1,#0x20] // mask all external interrupts | 86 | #if CONFIG_CPU==S5L8701 |
87 | str r0, [r1,#0x38] /* mask all external interrupts */ | ||
88 | str r0, [r1,#0x3c] | ||
89 | str r0, [r1,#0x40] | ||
90 | str r0, [r1,#0x44] | ||
91 | mvn r0, #0 | ||
92 | str r0, [r1,#0x28] /* clear pending external interrupts */ | ||
93 | str r0, [r1,#0x2c] | ||
94 | str r0, [r1,#0x30] | ||
95 | str r0, [r1,#0x34] | ||
96 | #else | ||
97 | str r0, [r1,#0x20] /* mask all external interrupts */ | ||
87 | mvn r0, #0 | 98 | mvn r0, #0 |
88 | str r0, [r1,#0x1c] // clear pending external interrupts | 99 | str r0, [r1,#0x1c] /* clear pending external interrupts */ |
89 | str r0, [r1] // irq priority | 100 | #endif |
90 | str r0, [r1,#0x10] // clear pending interrupts | 101 | str r0, [r1] /* irq priority */ |
102 | str r0, [r1,#0x10] /* clear pending interrupts */ | ||
91 | 103 | ||
92 | // ldr r1, =0x3cf00000 | 104 | // ldr r1, =0x3cf00000 |
93 | // ldr r0, [r1] | 105 | // ldr r0, [r1] |