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authorGreg White <gwhite@rockbox.org>2007-01-06 02:48:26 +0000
committerGreg White <gwhite@rockbox.org>2007-01-06 02:48:26 +0000
commit45bef7d914918113fa9e08f440cf80f27d9b2b46 (patch)
tree49f05e45550dec2bb5b9486f1d6fbe494da0cff3 /firmware/target
parentebcd762fb24455b58c9aab79a004e93d04a5c6cd (diff)
downloadrockbox-45bef7d914918113fa9e08f440cf80f27d9b2b46.tar.gz
rockbox-45bef7d914918113fa9e08f440cf80f27d9b2b46.zip
Fix range for cache cleans
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11928 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r--firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c b/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c
index 1e3412b2a0..36f653a9dd 100644
--- a/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c
+++ b/firmware/target/arm/gigabeat/meg-fx/mmu-meg-fx.c
@@ -87,15 +87,14 @@ static void enable_mmu(void) {
87/* Invalidate DCache for this range */ 87/* Invalidate DCache for this range */
88/* Will do write back */ 88/* Will do write back */
89void invalidate_dcache_range(const void *base, unsigned int size) { 89void invalidate_dcache_range(const void *base, unsigned int size) {
90 unsigned int addr = (int) base; 90 unsigned int addr = ((int) base) & ~31;
91 unsigned int end = addr+size; 91 unsigned int end = addr+size+32;
92 asm volatile( 92 asm volatile(
93 "bic %0, %0, #31 \n"
94"inv_start: \n" 93"inv_start: \n"
95 "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */ 94 "mcr p15, 0, %0, c7, c14, 1 \n" /* Clean and invalidate this line */
96 "add %0, %0, #32 \n" 95 "add %0, %0, #32 \n"
97 "cmp %0, %1 \n" 96 "cmp %0, %1 \n"
98 "blo inv_start \n" 97 "ble inv_start \n"
99 "mov %0, #0\n" 98 "mov %0, #0\n"
100 "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */ 99 "mcr p15,0,%0,c7,c10,4\n" /* Drain write buffer */
101 : : "r" (addr), "r" (end)); 100 : : "r" (addr), "r" (end));
@@ -105,7 +104,7 @@ void invalidate_dcache_range(const void *base, unsigned int size) {
105/* forces DCache writeback for the specified range */ 104/* forces DCache writeback for the specified range */
106void clean_dcache_range(const void *base, unsigned int size) { 105void clean_dcache_range(const void *base, unsigned int size) {
107 unsigned int addr = (int) base; 106 unsigned int addr = (int) base;
108 unsigned int end = addr+size; 107 unsigned int end = addr+size+32;
109 asm volatile( 108 asm volatile(
110 "bic %0, %0, #31 \n" 109 "bic %0, %0, #31 \n"
111"clean_start: \n" 110"clean_start: \n"