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author | Michael Sevakis <jethead71@rockbox.org> | 2009-02-03 12:16:45 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2009-02-03 12:16:45 +0000 |
commit | 3cf148945ed0b484b4610dbc2b4afaa34f2ce2cc (patch) | |
tree | 9d25dc10a7ab2f2a2d5dc263136ac121b6efd624 /firmware/target | |
parent | e2a169bce53aff3e5fc300c00d3828129298d469 (diff) | |
download | rockbox-3cf148945ed0b484b4610dbc2b4afaa34f2ce2cc.tar.gz rockbox-3cf148945ed0b484b4610dbc2b4afaa34f2ce2cc.zip |
Remove struct spinlock to cleanup some mess and simplify. It's only used in boosting for multiprocesors and a pure two-corelock heirarchy will do just fine.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19910 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/arm/system-pp502x.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/firmware/target/arm/system-pp502x.c b/firmware/target/arm/system-pp502x.c index d4c07f10eb..b1cef7152a 100644 --- a/firmware/target/arm/system-pp502x.c +++ b/firmware/target/arm/system-pp502x.c | |||
@@ -35,6 +35,10 @@ extern void SERIAL0(void); | |||
35 | extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */ | 35 | extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */ |
36 | extern void ipod_4g_button_int(void); /* iPod 4th gen and higher only */ | 36 | extern void ipod_4g_button_int(void); /* iPod 4th gen and higher only */ |
37 | 37 | ||
38 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | ||
39 | static struct corelock cpufreq_cl SHAREDBSS_ATTR; | ||
40 | #endif | ||
41 | |||
38 | void __attribute__((interrupt("IRQ"))) irq_handler(void) | 42 | void __attribute__((interrupt("IRQ"))) irq_handler(void) |
39 | { | 43 | { |
40 | if(CURRENT_CORE == CPU) | 44 | if(CURRENT_CORE == CPU) |
@@ -236,7 +240,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
236 | #endif | 240 | #endif |
237 | { | 241 | { |
238 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 242 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
239 | spinlock_lock(&boostctrl_spin); | 243 | corelock_lock(&cpufreq_cl); |
240 | #endif | 244 | #endif |
241 | 245 | ||
242 | switch (frequency) | 246 | switch (frequency) |
@@ -347,7 +351,7 @@ static void pp_set_cpu_frequency(long frequency) | |||
347 | } | 351 | } |
348 | 352 | ||
349 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) | 353 | #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1) |
350 | spinlock_unlock(&boostctrl_spin); | 354 | corelock_unlock(&cpufreq_cl); |
351 | #endif | 355 | #endif |
352 | } | 356 | } |
353 | #endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */ | 357 | #endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */ |
@@ -475,6 +479,7 @@ void system_init(void) | |||
475 | 479 | ||
476 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ | 480 | #ifdef HAVE_ADJUSTABLE_CPU_FREQ |
477 | #if NUM_CORES > 1 | 481 | #if NUM_CORES > 1 |
482 | corelock_init(&cpufreq_cl); | ||
478 | cpu_boost_init(); | 483 | cpu_boost_init(); |
479 | #endif | 484 | #endif |
480 | #else | 485 | #else |