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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-26 21:15:40 +0000 |
---|---|---|
committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-26 21:15:40 +0000 |
commit | 38436038a9e50e8314967672fb5e7b9a5009a4be (patch) | |
tree | de8509ed132bbc5a4c039b33950284d525f0485a /firmware/target | |
parent | 935fad7fd1bf16477447f0ff9745f5a72e3bfd62 (diff) | |
download | rockbox-38436038a9e50e8314967672fb5e7b9a5009a4be.tar.gz rockbox-38436038a9e50e8314967672fb5e7b9a5009a4be.zip |
Ingenic Jz4740:
* Add initial RoLo support
* Don't enable IRAM in plugins for now
* Initial try at getting PCM working (doesn't crash anymore at least)
* Replace hard-coded constant with #define in usb-jz4740
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20115 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/app.lds | 7 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/codec-jz4740.c | 28 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c | 71 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4740.c | 2 | ||||
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/usb-jz4740.c | 4 |
5 files changed, 83 insertions, 29 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/app.lds b/firmware/target/mips/ingenic_jz47xx/app.lds index dd539b0d41..37999c1050 100644 --- a/firmware/target/mips/ingenic_jz47xx/app.lds +++ b/firmware/target/mips/ingenic_jz47xx/app.lds | |||
@@ -12,10 +12,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o) | |||
12 | #define STUBOFFSET 0 | 12 | #define STUBOFFSET 0 |
13 | #endif | 13 | #endif |
14 | 14 | ||
15 | #define PLUGINSIZE PLUGIN_BUFFER_SIZE | 15 | #define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE - STUBOFFSET - CODEC_SIZE |
16 | #define CODECSIZE CODEC_SIZE | ||
17 | |||
18 | #define DRAMSIZE ((MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE) | ||
19 | 16 | ||
20 | #define DRAMORIG 0x80004000 | 17 | #define DRAMORIG 0x80004000 |
21 | #define IRAMORIG 0x80000000 | 18 | #define IRAMORIG 0x80000000 |
@@ -25,7 +22,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o) | |||
25 | #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) | 22 | #define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) |
26 | 23 | ||
27 | /* Where the codec buffer ends, and the plugin buffer starts */ | 24 | /* Where the codec buffer ends, and the plugin buffer starts */ |
28 | #define ENDADDR (ENDAUDIOADDR + CODECSIZE) | 25 | #define ENDADDR (ENDAUDIOADDR + CODEC_SIZE) |
29 | 26 | ||
30 | MEMORY | 27 | MEMORY |
31 | { | 28 | { |
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c index c76c63dd78..0b187be1cc 100644 --- a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c | |||
@@ -77,7 +77,7 @@ static void i2s_codec_init(void) | |||
77 | i2s_codec_reset(); | 77 | i2s_codec_reset(); |
78 | 78 | ||
79 | //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) | 79 | //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
80 | REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) | 80 | REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_44) |
81 | | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6)); | 81 | | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6)); |
82 | 82 | ||
83 | REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); | 83 | REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); |
@@ -98,7 +98,7 @@ static void i2s_codec_init(void) | |||
98 | 98 | ||
99 | REG_ICDC_CDCCR2 |= 3; | 99 | REG_ICDC_CDCCR2 |= 3; |
100 | 100 | ||
101 | HP_on_off_flag = 0; /* HP is off */ | 101 | HP_on_off_flag = 1; /* HP is on */ |
102 | } | 102 | } |
103 | 103 | ||
104 | static void i2s_codec_set_mic(unsigned short v) /* 0 <= v <= 100 */ | 104 | static void i2s_codec_set_mic(unsigned short v) /* 0 <= v <= 100 */ |
@@ -208,37 +208,36 @@ static void i2s_codec_set_samplerate(unsigned short rate) | |||
208 | switch (rate) | 208 | switch (rate) |
209 | { | 209 | { |
210 | case 8000: | 210 | case 8000: |
211 | speed = 0; | 211 | speed = 0 << 8; |
212 | break; | 212 | break; |
213 | case 11025: | 213 | case 11025: |
214 | speed = 1; | 214 | speed = 1 << 8; |
215 | break; | 215 | break; |
216 | case 12000: | 216 | case 12000: |
217 | speed = 2; | 217 | speed = 2 << 8; |
218 | break; | 218 | break; |
219 | case 16000: | 219 | case 16000: |
220 | speed = 3; | 220 | speed = 3 << 8; |
221 | break; | 221 | break; |
222 | case 22050: | 222 | case 22050: |
223 | speed = 4; | 223 | speed = 4 << 8; |
224 | break; | 224 | break; |
225 | case 24000: | 225 | case 24000: |
226 | speed = 5; | 226 | speed = 5 << 8; |
227 | break; | 227 | break; |
228 | case 32000: | 228 | case 32000: |
229 | speed = 6; | 229 | speed = 6 << 8; |
230 | break; | 230 | break; |
231 | case 44100: | 231 | case 44100: |
232 | speed = 7; | 232 | speed = 7 << 8; |
233 | break; | 233 | break; |
234 | case 48000: | 234 | case 48000: |
235 | speed = 8; | 235 | speed = 8 << 8; |
236 | break; | 236 | break; |
237 | default: | 237 | default: |
238 | break; | 238 | break; |
239 | } | 239 | } |
240 | REG_ICDC_CDCCR2 |= 0x00000f00; | 240 | REG_ICDC_CDCCR2 |= 0x00000f00; |
241 | speed = speed << 8; | ||
242 | 241 | ||
243 | speed |= 0xfffff0ff; | 242 | speed |= 0xfffff0ff; |
244 | REG_ICDC_CDCCR2 &= speed; | 243 | REG_ICDC_CDCCR2 &= speed; |
@@ -327,3 +326,8 @@ void audiohw_init(void) | |||
327 | { | 326 | { |
328 | i2s_codec_init(); | 327 | i2s_codec_init(); |
329 | } | 328 | } |
329 | |||
330 | void audiohw_set_frequency(int freq) | ||
331 | { | ||
332 | i2s_codec_set_samplerate(freq); | ||
333 | } | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c index b649311d13..c06c22e9c4 100644 --- a/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/pcm-jz4740.c | |||
@@ -32,13 +32,17 @@ | |||
32 | ** Playback DMA transfer | 32 | ** Playback DMA transfer |
33 | **/ | 33 | **/ |
34 | 34 | ||
35 | static bool playback_started = false; | ||
36 | static void* playback_address; | ||
35 | void pcm_postinit(void) | 37 | void pcm_postinit(void) |
36 | { | 38 | { |
37 | audiohw_postinit(); | 39 | audiohw_postinit(); |
38 | 40 | ||
39 | /* playback sample:16 bits, burst:16 bytes */ | 41 | /* playback sample: 16 bits burst: 16 bytes */ |
40 | __i2s_set_transmit_trigger(4); | 42 | __i2s_set_iss_sample_size(16); |
41 | __i2s_set_oss_sample_size(16); | 43 | __i2s_set_oss_sample_size(16); |
44 | __i2s_set_transmit_trigger(16 - 4); | ||
45 | __i2s_set_receive_trigger(4); | ||
42 | } | 46 | } |
43 | 47 | ||
44 | void pcm_play_dma_init(void) | 48 | void pcm_play_dma_init(void) |
@@ -54,15 +58,24 @@ void pcm_play_dma_init(void) | |||
54 | void pcm_dma_apply_settings(void) | 58 | void pcm_dma_apply_settings(void) |
55 | { | 59 | { |
56 | /* TODO */ | 60 | /* TODO */ |
61 | audiohw_set_frequency(pcm_fsel); | ||
57 | } | 62 | } |
58 | 63 | ||
59 | static void play_start_pcm(void) | 64 | static void play_start_pcm(void) |
60 | { | 65 | { |
66 | /* Prefill FIFO */ | ||
67 | REG_AIC_DR = 0; | ||
68 | REG_AIC_DR = 0; | ||
69 | REG_AIC_DR = 0; | ||
70 | REG_AIC_DR = 0; | ||
71 | |||
61 | __i2s_enable_transmit_dma(); | 72 | __i2s_enable_transmit_dma(); |
62 | __i2s_enable_replay(); | 73 | __i2s_enable_replay(); |
63 | 74 | ||
64 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN; | 75 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN; |
65 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) |= DMAC_DCMD_TIE; | 76 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) |= DMAC_DCMD_TIE; |
77 | |||
78 | playback_started = true; | ||
66 | } | 79 | } |
67 | 80 | ||
68 | static void play_stop_pcm(void) | 81 | static void play_stop_pcm(void) |
@@ -73,22 +86,52 @@ static void play_stop_pcm(void) | |||
73 | 86 | ||
74 | __i2s_disable_transmit_dma(); | 87 | __i2s_disable_transmit_dma(); |
75 | __i2s_disable_replay(); | 88 | __i2s_disable_replay(); |
89 | |||
90 | playback_started = false; | ||
76 | } | 91 | } |
77 | 92 | ||
78 | void pcm_play_dma_start(const void *addr, size_t size) | 93 | void pcm_play_dma_start(const void *addr, size_t size) |
79 | { | 94 | { |
80 | dma_enable(); | 95 | dma_enable(); |
81 | 96 | ||
97 | __dcache_writeback_all(); | ||
82 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES; | 98 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES; |
83 | REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr); | 99 | REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)addr); |
84 | REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); | 100 | REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); |
85 | REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size; | 101 | REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size; |
86 | REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT; | 102 | REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT; |
87 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI| DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_32); | 103 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_16); |
88 | 104 | ||
105 | playback_address = (void*)addr; | ||
89 | play_start_pcm(); | 106 | play_start_pcm(); |
90 | } | 107 | } |
91 | 108 | ||
109 | |||
110 | static void play_dma_callback(void) | ||
111 | { | ||
112 | unsigned char *start; | ||
113 | size_t size = 0; | ||
114 | |||
115 | pcm_callback_for_more(&start, &size); | ||
116 | if(size != 0) | ||
117 | { | ||
118 | __dcache_writeback_all(); | ||
119 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) = DMAC_DCCSR_NDES; | ||
120 | REG_DMAC_DSAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)start); | ||
121 | REG_DMAC_DTAR(DMA_AIC_TX_CHANNEL) = PHYSADDR((unsigned long)AIC_DR); | ||
122 | REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) = size; | ||
123 | REG_DMAC_DRSR(DMA_AIC_TX_CHANNEL) = DMAC_DRSR_RS_AICOUT; | ||
124 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) = (DMAC_DCMD_SAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DS_32BIT | DMAC_DCMD_DWDH_16); | ||
125 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) |= DMAC_DCCSR_EN; | ||
126 | REG_DMAC_DCMD(DMA_AIC_TX_CHANNEL) |= DMAC_DCMD_TIE; | ||
127 | return; | ||
128 | } | ||
129 | |||
130 | /* Error, callback missing or no more DMA to do */ | ||
131 | pcm_play_dma_stop(); | ||
132 | pcm_play_dma_stopped_callback(); | ||
133 | } | ||
134 | |||
92 | void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void) | 135 | void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void) |
93 | { | 136 | { |
94 | if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_AR) | 137 | if (REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) & DMAC_DCCSR_AR) |
@@ -101,21 +144,31 @@ void DMA_CALLBACK(DMA_AIC_TX_CHANNEL)(void) | |||
101 | { | 144 | { |
102 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~(DMAC_DCCSR_TT | DMAC_DCCSR_HLT); | 145 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~(DMAC_DCCSR_TT | DMAC_DCCSR_HLT); |
103 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_EN; | 146 | REG_DMAC_DCCSR(DMA_AIC_TX_CHANNEL) &= ~DMAC_DCCSR_EN; |
104 | __aic_disable_transmit_dma(); | 147 | play_dma_callback(); |
105 | } | 148 | } |
106 | } | 149 | } |
107 | 150 | ||
108 | size_t pcm_get_bytes_waiting(void) | 151 | size_t pcm_get_bytes_waiting(void) |
109 | { | 152 | { |
110 | return REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL); | 153 | if(playback_started) |
154 | return REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) & ~3; | ||
155 | else | ||
156 | return 0; | ||
111 | } | 157 | } |
112 | 158 | ||
113 | const void * pcm_play_dma_get_peak_buffer(int *count) | 159 | const void * pcm_play_dma_get_peak_buffer(int *count) |
114 | { | 160 | { |
115 | /* TODO */ | 161 | /* TODO */ |
116 | //*count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL)>>2; | 162 | if(playback_started) |
117 | *count = 0; | 163 | { |
118 | return NULL; | 164 | *count = REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL); |
165 | return (void*)(playback_address + ((REG_DMAC_DTCR(DMA_AIC_TX_CHANNEL) + 2) & ~3)); | ||
166 | } | ||
167 | else | ||
168 | { | ||
169 | *count = 0; | ||
170 | return NULL; | ||
171 | } | ||
119 | } | 172 | } |
120 | 173 | ||
121 | void pcm_play_dma_stop(void) | 174 | void pcm_play_dma_stop(void) |
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c index f78f3592e5..291716a309 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4740.c | |||
@@ -281,7 +281,7 @@ void dma_enable(void) | |||
281 | REG_DMAC_DCCSR(4) = 0; | 281 | REG_DMAC_DCCSR(4) = 0; |
282 | REG_DMAC_DCCSR(5) = 0; | 282 | REG_DMAC_DCCSR(5) = 0; |
283 | 283 | ||
284 | REG_DMAC_DMACR = (DMAC_DMACR_PR_012345 | DMAC_DMACR_DMAE); | 284 | REG_DMAC_DMACR = (DMAC_DMACR_PR_RR | DMAC_DMACR_DMAE); |
285 | } | 285 | } |
286 | } | 286 | } |
287 | 287 | ||
diff --git a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c index 2dd73c01a4..14656eed5f 100644 --- a/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/usb-jz4740.c | |||
@@ -730,7 +730,7 @@ int usb_drv_send_nonblocking(int endpoint, void* ptr, int length) | |||
730 | { | 730 | { |
731 | //dma_cache_wback_inv((unsigned long)ptr, length); | 731 | //dma_cache_wback_inv((unsigned long)ptr, length); |
732 | __dcache_writeback_all(); | 732 | __dcache_writeback_all(); |
733 | REG_USB_REG_ADDR1 = (unsigned long)ptr & 0x7fffffff; | 733 | REG_USB_REG_ADDR1 = PHYSADDR((unsigned long)ptr); |
734 | REG_USB_REG_COUNT1 = length; | 734 | REG_USB_REG_COUNT1 = length; |
735 | REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 | | 735 | REG_USB_REG_CNTL1 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 | |
736 | USB_CNTL_DIR_IN | USB_CNTL_ENA | | 736 | USB_CNTL_DIR_IN | USB_CNTL_ENA | |
@@ -780,7 +780,7 @@ int usb_drv_recv(int endpoint, void* ptr, int length) | |||
780 | { | 780 | { |
781 | //dma_cache_wback_inv((unsigned long)ptr, length); | 781 | //dma_cache_wback_inv((unsigned long)ptr, length); |
782 | __dcache_writeback_all(); | 782 | __dcache_writeback_all(); |
783 | REG_USB_REG_ADDR2 = (unsigned long)ptr & 0x7fffffff; | 783 | REG_USB_REG_ADDR2 = PHYSADDR((unsigned long)ptr); |
784 | REG_USB_REG_COUNT2 = length; | 784 | REG_USB_REG_COUNT2 = length; |
785 | REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 | | 785 | REG_USB_REG_CNTL2 = (USB_CNTL_INTR_EN | USB_CNTL_MODE_1 | |
786 | USB_CNTL_ENA | USB_CNTL_EP(endpoint) | | 786 | USB_CNTL_ENA | USB_CNTL_EP(endpoint) | |