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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 10:41:00 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 10:41:41 -0400 |
commit | 1aee1683987e37196e9b188eb45c01e96a4a3f28 (patch) | |
tree | da356479821dc82516302f3cc25386d25fbebb49 /firmware/target | |
parent | 5fb4c74bfb16f2dcf1249b04c491526ca89b1fad (diff) | |
download | rockbox-1aee1683987e37196e9b188eb45c01e96a4a3f28.tar.gz rockbox-1aee1683987e37196e9b188eb45c01e96a4a3f28.zip |
jz4760: Pull non-PLL init out of pll0_init() code.
So it only gets called once, at system startup.
Change-Id: I4c191519009e80dfb118065391295c88a014d25a
Diffstat (limited to 'firmware/target')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 899b346b54..d94bea3f00 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -470,11 +470,6 @@ static void pll0_init(unsigned int freq) | |||
470 | else | 470 | else |
471 | offset = 0; | 471 | offset = 0; |
472 | 472 | ||
473 | /* set ahb **/ | ||
474 | REG32(HARB0_BASE) = 0x00300000; | ||
475 | REG32(0xb3070048) = 0x00000000; | ||
476 | REG32(HARB2_BASE) = 0x00FFFFFF; | ||
477 | |||
478 | cfcr = CPCCR_PCS | // no divisor on PLL for peripherals | 473 | cfcr = CPCCR_PCS | // no divisor on PLL for peripherals |
479 | (n2FR[div[offset][0]] << CPCCR_CDIV_LSB) | | 474 | (n2FR[div[offset][0]] << CPCCR_CDIV_LSB) | |
480 | (n2FR[div[offset][1]] << CPCCR_HDIV_LSB) | | 475 | (n2FR[div[offset][1]] << CPCCR_HDIV_LSB) | |
@@ -483,16 +478,6 @@ static void pll0_init(unsigned int freq) | |||
483 | (n2FR[div[offset][4]] << CPCCR_MDIV_LSB) | | 478 | (n2FR[div[offset][4]] << CPCCR_MDIV_LSB) | |
484 | (n2FR[div[offset][5]] << CPCCR_SDIV_LSB); | 479 | (n2FR[div[offset][5]] << CPCCR_SDIV_LSB); |
485 | 480 | ||
486 | // write REG_DDRC_CTRL 8 times to clear ddr fifo | ||
487 | REG_DDRC_CTRL = 0; | ||
488 | REG_DDRC_CTRL = 0; | ||
489 | REG_DDRC_CTRL = 0; | ||
490 | REG_DDRC_CTRL = 0; | ||
491 | REG_DDRC_CTRL = 0; | ||
492 | REG_DDRC_CTRL = 0; | ||
493 | REG_DDRC_CTRL = 0; | ||
494 | REG_DDRC_CTRL = 0; | ||
495 | |||
496 | if (CFG_EXTAL > 16000000) | 481 | if (CFG_EXTAL > 16000000) |
497 | cfcr |= CPCCR_ECS; | 482 | cfcr |= CPCCR_ECS; |
498 | else | 483 | else |
@@ -692,6 +677,21 @@ void ICODE_ATTR system_main(void) | |||
692 | 677 | ||
693 | mmu_init(); | 678 | mmu_init(); |
694 | 679 | ||
680 | /* set ahb arbitrators */ | ||
681 | REG32(HARB0_BASE) = 0x00300000; /* HARB0_PRIOR [bridge, cim, lcd, ipu] */ | ||
682 | REG32(0xb3070048) = 0x00000000; /* Not documented! */ | ||
683 | REG32(HARB2_BASE) = 0x00FFFFFF; /* HARB2_PRIOR [p0b, gps, uhc],[eth, dma, p1br, otg] */ | ||
684 | |||
685 | /* write REG_DDRC_CTRL 8 times to clear ddr fifo */ | ||
686 | REG_DDRC_CTRL = 0; | ||
687 | REG_DDRC_CTRL = 0; | ||
688 | REG_DDRC_CTRL = 0; | ||
689 | REG_DDRC_CTRL = 0; | ||
690 | REG_DDRC_CTRL = 0; | ||
691 | REG_DDRC_CTRL = 0; | ||
692 | REG_DDRC_CTRL = 0; | ||
693 | REG_DDRC_CTRL = 0; | ||
694 | |||
695 | pll0_init(CPUFREQ_DEFAULT); // PLL0 drives everything but audio | 695 | pll0_init(CPUFREQ_DEFAULT); // PLL0 drives everything but audio |
696 | pll1_disable(); // Leave PLL1 disabled until audio needs it | 696 | pll1_disable(); // Leave PLL1 disabled until audio needs it |
697 | 697 | ||
@@ -770,7 +770,6 @@ void set_cpu_frequency(long frequency) | |||
770 | frequency = CPUFREQ_MAX; | 770 | frequency = CPUFREQ_MAX; |
771 | 771 | ||
772 | pll0_init(frequency); | 772 | pll0_init(frequency); |
773 | // FIX PCLK (ie i2c)? | ||
774 | cpu_frequency = __cpm_get_pllout2(); | 773 | cpu_frequency = __cpm_get_pllout2(); |
775 | cpm_select_msc_clk(); | 774 | cpm_select_msc_clk(); |
776 | } | 775 | } |