D2: Enable ARM cache coherency functions (eg. during codec load), which should eliminate data aborts/freezes on track changes. NOTE: The linker script reserves space at the end of DRAM for the TTB, but this is not currently used.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22595 a1c6a512-1295-4272-9138-f99709370657

2 files changed, 3 insertions, 1 deletions

diff --git a/firmware/target/arm/tcc780x/app.lds b/firmware/target/arm/tcc780x/app.lds
index d62204a9a5..a742908ce1 100644
--- a/firmware/target/arm/tcc780x/app.lds
+++ b/firmware/target/arm/tcc780x/app.lds
@@ -15,7 +15,8 @@ STARTUP(target/arm/tcc780x/crt0.o)
 #define STUBOFFSET 0
 #endif
 
-#define DRAMSIZE (MEMORYSIZE * 0x100000) - PLUGINSIZE - STUBOFFSET - CODECSIZE
+#include "cpu.h"
+#define DRAMSIZE (MEMORYSIZE * 0x100000) - STUBOFFSET - PLUGINSIZE - CODECSIZE - TTB_SIZE
 
 #define DRAMORIG 0x20000000 + STUBOFFSET
 #define ITCMORIG 0x00000000
diff --git a/firmware/target/arm/tcc780x/system-target.h b/firmware/target/arm/tcc780x/system-target.h
index 6e2e7be980..fe66a6eb68 100644
--- a/firmware/target/arm/tcc780x/system-target.h
+++ b/firmware/target/arm/tcc780x/system-target.h
@@ -22,6 +22,7 @@
 #define SYSTEM_TARGET_H
 
 #include "system-arm.h"
+#include "mmu-arm.h"
 
 #define CPUFREQ_DEFAULT 32000000
 #define CPUFREQ_NORMAL  48000000