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| author | Amaury Pouly <amaury.pouly@gmail.com> | 2012-02-28 22:45:45 +0100 |
|---|---|---|
| committer | Amaury Pouly <amaury.pouly@gmail.com> | 2012-02-28 23:57:37 +0100 |
| commit | 0d78dd170d459ca0cce6c1f107ea0a98066f3a62 (patch) | |
| tree | 7a246316ea60f7175f073a739122fed4befcb9e3 /firmware/target | |
| parent | c4450b9baf0b09d1da054f282603573547b7ad14 (diff) | |
| download | rockbox-0d78dd170d459ca0cce6c1f107ea0a98066f3a62.tar.gz rockbox-0d78dd170d459ca0cce6c1f107ea0a98066f3a62.zip | |
imx233: user __FIELD_SET to set the clock divisors
The clock divisors must *NEVER* be 0, first clearing then setting is thus undefined.
Change-Id: Iba8e6ba1e668bf746e3f7387f0175f63d81f6b2b
Diffstat (limited to 'firmware/target')
| -rw-r--r-- | firmware/target/arm/imx233/clkctrl-imx233.c | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/firmware/target/arm/imx233/clkctrl-imx233.c b/firmware/target/arm/imx233/clkctrl-imx233.c index 744a4b11d8..bfa707e3be 100644 --- a/firmware/target/arm/imx233/clkctrl-imx233.c +++ b/firmware/target/arm/imx233/clkctrl-imx233.c | |||
| @@ -80,34 +80,22 @@ void imx233_set_clock_divisor(enum imx233_clock_t clk, int div) | |||
| 80 | switch(clk) | 80 | switch(clk) |
| 81 | { | 81 | { |
| 82 | case CLK_PIX: | 82 | case CLK_PIX: |
| 83 | HW_CLKCTRL_PIX &= ~HW_CLKCTRL_PIX__DIV_BM; | 83 | __FIELD_SET(HW_CLKCTRL_PIX, DIV, div); |
| 84 | HW_CLKCTRL_PIX |= div; | ||
| 85 | while(HW_CLKCTRL_PIX & __CLK_BUSY); | ||
| 86 | break; | 84 | break; |
| 87 | case CLK_SSP: | 85 | case CLK_SSP: |
| 88 | HW_CLKCTRL_SSP &= ~HW_CLKCTRL_SSP__DIV_BM; | 86 | __FIELD_SET(HW_CLKCTRL_SSP, DIV, div); |
| 89 | HW_CLKCTRL_SSP |= div; | ||
| 90 | while(HW_CLKCTRL_SSP & __CLK_BUSY); | ||
| 91 | break; | 87 | break; |
| 92 | case CLK_CPU: | 88 | case CLK_CPU: |
| 93 | __REG_CLR(HW_CLKCTRL_CPU) = HW_CLKCTRL_CPU__DIV_CPU_BM; | 89 | __FIELD_SET(HW_CLKCTRL_CPU, DIV_CPU, div); |
| 94 | __REG_SET(HW_CLKCTRL_CPU) = div; | ||
| 95 | while(HW_CLKCTRL_CPU & HW_CLKCTRL_CPU__BUSY_REF_CPU); | ||
| 96 | break; | 90 | break; |
| 97 | case CLK_EMI: | 91 | case CLK_EMI: |
| 98 | HW_CLKCTRL_EMI &= ~HW_CLKCTRL_EMI__DIV_EMI_BM; | 92 | __FIELD_SET(HW_CLKCTRL_EMI, DIV_EMI, div); |
| 99 | HW_CLKCTRL_EMI |= div; | ||
| 100 | while(HW_CLKCTRL_EMI & HW_CLKCTRL_EMI__BUSY_REF_EMI); | ||
| 101 | break; | 93 | break; |
| 102 | case CLK_HBUS: | 94 | case CLK_HBUS: |
| 103 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__DIV_BM | HW_CLKCTRL_HBUS__DIV_FRAC_EN; | 95 | __FIELD_SET(HW_CLKCTRL_HBUS, DIV, div); |
| 104 | __REG_SET(HW_CLKCTRL_HBUS) = div; | ||
| 105 | while(HW_CLKCTRL_HBUS & __CLK_BUSY); | ||
| 106 | break; | 96 | break; |
| 107 | case CLK_XBUS: | 97 | case CLK_XBUS: |
| 108 | HW_CLKCTRL_XBUS &= ~HW_CLKCTRL_XBUS__DIV_BM; | 98 | __FIELD_SET(HW_CLKCTRL_XBUS, DIV, div); |
| 109 | HW_CLKCTRL_XBUS |= div; | ||
| 110 | while(HW_CLKCTRL_XBUS & __CLK_BUSY); | ||
| 111 | break; | 99 | break; |
| 112 | default: return; | 100 | default: return; |
| 113 | } | 101 | } |
| @@ -138,8 +126,8 @@ void imx233_set_fractional_divisor(enum imx233_clock_t clk, int fracdiv) | |||
| 138 | switch(clk) | 126 | switch(clk) |
| 139 | { | 127 | { |
| 140 | case CLK_HBUS: | 128 | case CLK_HBUS: |
| 141 | __REG_CLR(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__DIV_BM; | 129 | __FIELD_SET(HW_CLKCTRL_HBUS, DIV, fracdiv); |
| 142 | __REG_SET(HW_CLKCTRL_HBUS) = fracdiv | HW_CLKCTRL_HBUS__DIV_FRAC_EN; | 130 | __REG_SET(HW_CLKCTRL_HBUS) = HW_CLKCTRL_HBUS__DIV_FRAC_EN; |
| 143 | return; | 131 | return; |
| 144 | case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; | 132 | case CLK_PIX: REG = &HW_CLKCTRL_FRAC_PIX; break; |
| 145 | case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; | 133 | case CLK_IO: REG = &HW_CLKCTRL_FRAC_IO; break; |