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authorSolomon Peachy <pizza@shaftnet.org>2020-08-29 23:38:56 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-08-30 01:45:15 -0400
commitcc5b0439a8f05afbb48a868e97ca9f196f5a8404 (patch)
tree1d7d192d2a926f7c748a4bcd1b917c1b09f70d5e /firmware/target/mips
parentb01e9295e4b5ae2680dc4a8acaf9349250cd6b8d (diff)
downloadrockbox-cc5b0439a8f05afbb48a868e97ca9f196f5a8404.tar.gz
rockbox-cc5b0439a8f05afbb48a868e97ca9f196f5a8404.zip
jz4760: Prioritize Audio DMA and TCU0 (systick) above all others
(And loop in the IRQ handler to make sure we catch everything!) Change-Id: I813272c69e981fdc214ec28448ced403ad366ea0
Diffstat (limited to 'firmware/target/mips')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-jz4760.c44
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h16
2 files changed, 21 insertions, 39 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
index 01d6d8d93e..4489212ccc 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
+++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c
@@ -244,41 +244,20 @@ static int get_irq_number(void)
244 if (UNLIKELY(irq0 < 0) && UNLIKELY(irq1 < 0)) 244 if (UNLIKELY(irq0 < 0) && UNLIKELY(irq1 < 0))
245 return -1; 245 return -1;
246 246
247#if 1 247 // Prioritze DMA0 (audio) and TCU0 (systick), then everything on ipl1 (ie MSC mostly)
248 // Prioritze AIC and SADC, then everything on ipl1 (ie MSC mostly) 248 if (ipl0 & 1<<IRQ_DMAC0) {
249 if (ipl1 & 1<<(IRQ_AIC-32)) { 249 irq = IRQ_DMAC0;
250 irq = IRQ_AIC; 250 ipl0 &= ~(1<<IRQ_DMAC0);
251 ipl1 &= ~(1<<(IRQ_AIC-32)); 251 } else if (ipl0 & 1<<IRQ_TCU0) {
252 } else if (ipl0 & 1<<IRQ_SADC) { 252 irq = IRQ_TCU0;
253 irq = IRQ_SADC; 253 ipl0 &= ~(1<<IRQ_TCU0);
254 ipl0 &= ~(1<<IRQ_SADC);
255 } else if (ipl1) { 254 } else if (ipl1) {
256 irq = irq1 + 32; 255 irq = irq1 + 32;
257 ipl1 &= ~(1<<irq1); 256 ipl1 &= ~(1<<irq1);
258 } else { 257 } else {
259 irq = irq0; 258 irq = irq0;
260 ipl0 &= ~(1<<irq0); 259 ipl0 &= ~(1<<irq0);
261 } 260 }
262#else
263 // Prioritize I2C0, I2C1, IPL0, and finally IPL1
264 if (!(ipl0 & 3)) {
265 if (ipl0) {
266 irq = irq0;
267 ipl0 &= ~(1<<irq0);
268 } else {
269 irq = irq1 + 32;
270 ipl1 &= ~(1<<irq1);
271 }
272 } else {
273 if (ipl0 & 2) {
274 irq = 1;
275 ipl0 &= ~(1<<irq);
276 } else {
277 irq = 0;
278 ipl0 &= ~(1<<irq);
279 }
280 }
281#endif
282 261
283 switch (irq) 262 switch (irq)
284 { 263 {
@@ -307,13 +286,16 @@ static int get_irq_number(void)
307 286
308void intr_handler(void) 287void intr_handler(void)
309{ 288{
310 register int irq = get_irq_number(); 289 register int irq;
290top:
291 irq = get_irq_number();
311 if(UNLIKELY(irq < 0)) 292 if(UNLIKELY(irq < 0))
312 return; 293 return;
313 294
314 ack_irq(irq); 295 ack_irq(irq);
315 if(LIKELY(irq >= 0)) 296 if(LIKELY(irq >= 0))
316 irqvector[irq](); 297 irqvector[irq]();
298 goto top;
317} 299}
318 300
319#define EXC(x,y) case (x): return (y); 301#define EXC(x,y) case (x): return (y);
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index b6e779ea53..dd42fac633 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -95,15 +95,15 @@ void dma_disable(void);
95#define DMA_LCD_CHANNEL 3 95#define DMA_LCD_CHANNEL 3
96#elif CONFIG_CPU == JZ4760B 96#elif CONFIG_CPU == JZ4760B
97#define DMA_AIC_TX_CHANNEL 0 97#define DMA_AIC_TX_CHANNEL 0
98#define DMA_NAND_CHANNEL 1 98#define DMA_USB_CHANNEL 1
99#define DMA_USB_CHANNEL 2
100#define DMA_SD_RX_CHANNEL0 3
101#define DMA_SD_RX_CHANNEL1 4
102// Note: channel 5 and 11 cannot be used! 99// Note: channel 5 and 11 cannot be used!
103#define DMA_SD_TX_CHANNEL0 6 100#define DMA_SD_RX_CHANNEL0 6
104#define DMA_SD_TX_CHANNEL1 7 101#define DMA_SD_RX_CHANNEL1 7
105#define DMA_SD_RX_CHANNEL(n) 3+n 102#define DMA_SD_TX_CHANNEL0 8
106#define DMA_SD_TX_CHANNEL(n) 6+n 103#define DMA_SD_TX_CHANNEL1 9
104#define DMA_NAND_CHANNEL 10
105#define DMA_SD_RX_CHANNEL(n) 6+n
106#define DMA_SD_TX_CHANNEL(n) 8+n
107#endif 107#endif
108 108
109#define XDMA_CALLBACK(n) DMA ## n 109#define XDMA_CALLBACK(n) DMA ## n