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| author | William Wilgus <wilgus.william@gmail.com> | 2021-03-29 10:04:04 -0400 |
|---|---|---|
| committer | William Wilgus <wilgus.william@gmail.com> | 2021-04-01 00:52:57 -0400 |
| commit | 89acde6af2c9d8ff4a647e7abd737b18333cad80 (patch) | |
| tree | 92c9ec13b6292c1cbc2abf6b0692fff49e95cd02 /firmware/target/mips | |
| parent | 058a9ec9453fed05872d10c72913bbc7034d32d8 (diff) | |
| download | rockbox-89acde6af2c9d8ff4a647e7abd737b18333cad80.tar.gz rockbox-89acde6af2c9d8ff4a647e7abd737b18333cad80.zip | |
H10 PP Crash -- Fixed
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Diffstat (limited to 'firmware/target/mips')
0 files changed, 0 insertions, 0 deletions