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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-28 21:45:58 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-03 15:34:28 -0400 |
commit | 0cb162a76b16d58250a33e817af6a763e89a770a (patch) | |
tree | af5ac50c1ec59f665e0a4845672a16d758b44953 /firmware/target/mips/mmu-mips.h | |
parent | 1ae8213a64c23ac86173b8139e01c7cad350ec6b (diff) | |
download | rockbox-0cb162a76b16d58250a33e817af6a763e89a770a.tar.gz rockbox-0cb162a76b16d58250a33e817af6a763e89a770a.zip |
mips: Heavily rework DMA & caching code
Based on code originally written by Amaury Pouly (g#1789, g#1791, g#1527)
but rebased and heavily updated.
Change-Id: Ic794abb5e8d89feb4b88fc3abe854270fb28db70
Diffstat (limited to 'firmware/target/mips/mmu-mips.h')
-rw-r--r-- | firmware/target/mips/mmu-mips.h | 34 |
1 files changed, 20 insertions, 14 deletions
diff --git a/firmware/target/mips/mmu-mips.h b/firmware/target/mips/mmu-mips.h index 7e1e36d3f4..f96ddcc28d 100644 --- a/firmware/target/mips/mmu-mips.h +++ b/firmware/target/mips/mmu-mips.h | |||
@@ -28,19 +28,25 @@ void map_address(unsigned long virtual, unsigned long physical, | |||
28 | unsigned long length, unsigned int cache_flags); | 28 | unsigned long length, unsigned int cache_flags); |
29 | void mmu_init(void); | 29 | void mmu_init(void); |
30 | 30 | ||
31 | #define HAVE_CPUCACHE_INVALIDATE | 31 | /* Commits entire DCache */ |
32 | //#define HAVE_CPUCACHE_FLUSH | 32 | void commit_dcache(void); |
33 | 33 | /* Commit and discard entire DCache, will do writeback */ | |
34 | void __idcache_invalidate_all(void); | 34 | void commit_discard_dcache(void); |
35 | void __icache_invalidate_all(void); | 35 | |
36 | void __dcache_invalidate_all(void); | 36 | /* Write DCache back to RAM for the given range and remove cache lines |
37 | void __dcache_writeback_all(void); | 37 | * from DCache afterwards */ |
38 | 38 | void commit_discard_dcache_range(const void *base, unsigned int size); | |
39 | void dma_cache_wback_inv(unsigned long addr, unsigned long size); | 39 | |
40 | 40 | /* Write DCache back to RAM for the given range */ | |
41 | #define commit_discard_idcache __idcache_invalidate_all | 41 | void commit_dcache_range(const void *base, unsigned int size); |
42 | #define commit_discard_icache __icache_invalidate_all | 42 | |
43 | #define commit_discard_dcache __dcache_invalidate_all | 43 | /* |
44 | #define commit_dcache __dcache_writeback_all | 44 | * Remove cache lines for the given range from DCache |
45 | * will *NOT* do write back except for buffer edges not on a line boundary | ||
46 | */ | ||
47 | void discard_dcache_range(const void *base, unsigned int size); | ||
48 | |||
49 | /* Discards the entire ICache, and commit+discards the entire DCache */ | ||
50 | void commit_discard_idcache(void); | ||
45 | 51 | ||
46 | #endif /* __MMU_MIPS_INCLUDE_H */ | 52 | #endif /* __MMU_MIPS_INCLUDE_H */ |