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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-04 17:33:19 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2009-02-04 17:33:19 +0000 |
commit | 9b13a5d151a14ba7a5b8c502763cb56356260ceb (patch) | |
tree | 854f056a73a8eceb06ce08a3a74de75121b37350 /firmware/target/mips/mmu-mips.c | |
parent | 01bd736e000856ded49023ccdd4ed62b96f300ff (diff) | |
download | rockbox-9b13a5d151a14ba7a5b8c502763cb56356260ceb.tar.gz rockbox-9b13a5d151a14ba7a5b8c502763cb56356260ceb.zip |
MIPS:
* Add assembly optimised variants for memcpy, memset and find_first_set_bit
* Add option to map_address in MMU to set caching algorithm
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19920 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/mmu-mips.c')
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 3c1b932325..570b209e3a 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -99,14 +99,15 @@ static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
99 | restore_irq(old_irq); | 99 | restore_irq(old_irq); |
100 | } | 100 | } |
101 | 101 | ||
102 | void map_address(unsigned long virtual, unsigned long physical, unsigned long length) | 102 | void map_address(unsigned long virtual, unsigned long physical, |
103 | unsigned long length, unsigned int cache_flags) | ||
103 | { | 104 | { |
104 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; | 105 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; |
105 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; | 106 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; |
106 | unsigned long entryhi = virtual & ~VPN2_SHIFT; | 107 | unsigned long entryhi = virtual & ~VPN2_SHIFT; |
107 | 108 | ||
108 | entry0 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) ); | 109 | entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
109 | entry1 |= (M_EntryLoG | M_EntryLoV | (K_CacheAttrC << S_EntryLoC) ); | 110 | entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
110 | 111 | ||
111 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); | 112 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); |
112 | } | 113 | } |
@@ -119,7 +120,7 @@ void tlb_init(void) | |||
119 | 120 | ||
120 | local_flush_tlb_all(); | 121 | local_flush_tlb_all(); |
121 | /* | 122 | /* |
122 | map_address(0x80000000, 0x80000000, 0x4000); | 123 | map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC); |
123 | map_address(0x80004000, 0x80004000, MEM * 0x100000); | 124 | map_address(0x80004000, 0x80004000, MEM * 0x100000, K_CacheAttrC); |
124 | */ | 125 | */ |
125 | } | 126 | } |