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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-02-27 22:08:58 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-28 00:01:37 +0000 |
commit | 3ec66893e377b088c1284d2d23adb2aeea6d7965 (patch) | |
tree | b647717f83ad56b15dc42cfdef5d04d68cd9bd6b /firmware/target/mips/mmu-mips.c | |
parent | 83fcbedc65f4b9ae7e491ecf6f07c0af4b245f74 (diff) | |
download | rockbox-3ec66893e377b088c1284d2d23adb2aeea6d7965.tar.gz rockbox-3ec66893e377b088c1284d2d23adb2aeea6d7965.zip |
New port: FiiO M3K on bare metal
Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
Diffstat (limited to 'firmware/target/mips/mmu-mips.c')
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index 2daed5ed9e..f4770aa468 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "system.h" | 25 | #include "system.h" |
26 | #include "mmu-mips.h" | 26 | #include "mmu-mips.h" |
27 | 27 | ||
28 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 28 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B || CONFIG_CPU == X1000 |
29 | /* XBurst core has 32 JTLB entries */ | 29 | /* XBurst core has 32 JTLB entries */ |
30 | #define NR_TLB_ENTRIES 32 | 30 | #define NR_TLB_ENTRIES 32 |
31 | #else | 31 | #else |
@@ -134,7 +134,7 @@ void mmu_init(void) | |||
134 | /* Target specific operations: | 134 | /* Target specific operations: |
135 | * - invalidate BTB (Branch Table Buffer) | 135 | * - invalidate BTB (Branch Table Buffer) |
136 | * - sync barrier after cache operations */ | 136 | * - sync barrier after cache operations */ |
137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B | 137 | #if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B || CONFIG_CPU == X1000 |
138 | #define INVALIDATE_BTB() \ | 138 | #define INVALIDATE_BTB() \ |
139 | do { \ | 139 | do { \ |
140 | register unsigned long tmp; \ | 140 | register unsigned long tmp; \ |