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author | William Wilgus <wilgus.william@gmail.com> | 2020-08-29 10:14:03 -0400 |
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committer | William Wilgus <wilgus.william@gmail.com> | 2020-08-29 10:14:03 -0400 |
commit | 3867f0b95958a6219ed5b459c22b246fb827efe2 (patch) | |
tree | 76d3677f5cd31108d0449603506569433543bbc7 /firmware/target/mips/mmu-mips.c | |
parent | 6296b220e5408feda177346a5a439ce4c6803a83 (diff) | |
download | rockbox-3867f0b95958a6219ed5b459c22b246fb827efe2.tar.gz rockbox-3867f0b95958a6219ed5b459c22b246fb827efe2.zip |
XduooX3 Sources WS changes
Change-Id: I17ae59e7ef0440756527ce50ab30f8bf34f79007
Diffstat (limited to 'firmware/target/mips/mmu-mips.c')
-rw-r--r-- | firmware/target/mips/mmu-mips.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/firmware/target/mips/mmu-mips.c b/firmware/target/mips/mmu-mips.c index b519bf9331..552348014e 100644 --- a/firmware/target/mips/mmu-mips.c +++ b/firmware/target/mips/mmu-mips.c | |||
@@ -48,7 +48,7 @@ static void local_flush_tlb_all(void) | |||
48 | unsigned long old_ctx; | 48 | unsigned long old_ctx; |
49 | int entry; | 49 | int entry; |
50 | unsigned int old_irq = disable_irq_save(); | 50 | unsigned int old_irq = disable_irq_save(); |
51 | 51 | ||
52 | /* Save old context and create impossible VPN2 value */ | 52 | /* Save old context and create impossible VPN2 value */ |
53 | old_ctx = read_c0_entryhi(); | 53 | old_ctx = read_c0_entryhi(); |
54 | write_c0_entrylo0(0); | 54 | write_c0_entrylo0(0); |
@@ -66,7 +66,7 @@ static void local_flush_tlb_all(void) | |||
66 | } | 66 | } |
67 | BARRIER; | 67 | BARRIER; |
68 | write_c0_entryhi(old_ctx); | 68 | write_c0_entryhi(old_ctx); |
69 | 69 | ||
70 | restore_irq(old_irq); | 70 | restore_irq(old_irq); |
71 | } | 71 | } |
72 | 72 | ||
@@ -77,7 +77,7 @@ static void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
77 | unsigned long old_pagemask; | 77 | unsigned long old_pagemask; |
78 | unsigned long old_ctx; | 78 | unsigned long old_ctx; |
79 | unsigned int old_irq = disable_irq_save(); | 79 | unsigned int old_irq = disable_irq_save(); |
80 | 80 | ||
81 | old_ctx = read_c0_entryhi() & ASID_MASK; | 81 | old_ctx = read_c0_entryhi() & ASID_MASK; |
82 | old_pagemask = read_c0_pagemask(); | 82 | old_pagemask = read_c0_pagemask(); |
83 | wired = read_c0_wired(); | 83 | wired = read_c0_wired(); |
@@ -105,10 +105,10 @@ void map_address(unsigned long virtual, unsigned long physical, | |||
105 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; | 105 | unsigned long entry0 = (physical & PFN_MASK) << PFN_SHIFT; |
106 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; | 106 | unsigned long entry1 = ((physical+length) & PFN_MASK) << PFN_SHIFT; |
107 | unsigned long entryhi = virtual & ~VPN2_SHIFT; | 107 | unsigned long entryhi = virtual & ~VPN2_SHIFT; |
108 | 108 | ||
109 | entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); | 109 | entry0 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
110 | entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); | 110 | entry1 |= (M_EntryLoG | M_EntryLoV | (cache_flags << S_EntryLoC) ); |
111 | 111 | ||
112 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); | 112 | add_wired_entry(entry0, entry1, entryhi, DEFAULT_PAGE_MASK); |
113 | } | 113 | } |
114 | 114 | ||
@@ -117,7 +117,7 @@ void mmu_init(void) | |||
117 | write_c0_pagemask(DEFAULT_PAGE_MASK); | 117 | write_c0_pagemask(DEFAULT_PAGE_MASK); |
118 | write_c0_wired(0); | 118 | write_c0_wired(0); |
119 | write_c0_framemask(0); | 119 | write_c0_framemask(0); |
120 | 120 | ||
121 | local_flush_tlb_all(); | 121 | local_flush_tlb_all(); |
122 | /* | 122 | /* |
123 | map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC); | 123 | map_address(0x80000000, 0x80000000, 0x4000, K_CacheAttrC); |