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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-02-27 22:08:58 +0000 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-03-28 00:01:37 +0000 |
commit | 3ec66893e377b088c1284d2d23adb2aeea6d7965 (patch) | |
tree | b647717f83ad56b15dc42cfdef5d04d68cd9bd6b /firmware/target/mips/ingenic_x1000/x1000/ddrc.h | |
parent | 83fcbedc65f4b9ae7e491ecf6f07c0af4b245f74 (diff) | |
download | rockbox-3ec66893e377b088c1284d2d23adb2aeea6d7965.tar.gz rockbox-3ec66893e377b088c1284d2d23adb2aeea6d7965.zip |
New port: FiiO M3K on bare metal
Change-Id: I7517e7d5459e129dcfc9465c6fbd708619888fbe
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/x1000/ddrc.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/x1000/ddrc.h | 149 |
1 files changed, 149 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/x1000/ddrc.h b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h new file mode 100644 index 0000000000..f482969a4e --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/x1000/ddrc.h | |||
@@ -0,0 +1,149 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * This file was automatically generated by headergen, DO NOT EDIT it. | ||
9 | * headergen version: 3.0.0 | ||
10 | * x1000 version: 1.0 | ||
11 | * x1000 authors: Aidan MacDonald | ||
12 | * | ||
13 | * Copyright (C) 2015 by the authors | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or | ||
16 | * modify it under the terms of the GNU General Public License | ||
17 | * as published by the Free Software Foundation; either version 2 | ||
18 | * of the License, or (at your option) any later version. | ||
19 | * | ||
20 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
21 | * KIND, either express or implied. | ||
22 | * | ||
23 | ****************************************************************************/ | ||
24 | #ifndef __HEADERGEN_DDRC_H__ | ||
25 | #define __HEADERGEN_DDRC_H__ | ||
26 | |||
27 | #include "macro.h" | ||
28 | |||
29 | #define REG_DDRC_STATUS jz_reg(DDRC_STATUS) | ||
30 | #define JA_DDRC_STATUS (0xb34f0000 + 0x0) | ||
31 | #define JT_DDRC_STATUS JIO_32_RW | ||
32 | #define JN_DDRC_STATUS DDRC_STATUS | ||
33 | #define JI_DDRC_STATUS | ||
34 | |||
35 | #define REG_DDRC_CFG jz_reg(DDRC_CFG) | ||
36 | #define JA_DDRC_CFG (0xb34f0000 + 0x4) | ||
37 | #define JT_DDRC_CFG JIO_32_RW | ||
38 | #define JN_DDRC_CFG DDRC_CFG | ||
39 | #define JI_DDRC_CFG | ||
40 | |||
41 | #define REG_DDRC_CTRL jz_reg(DDRC_CTRL) | ||
42 | #define JA_DDRC_CTRL (0xb34f0000 + 0x8) | ||
43 | #define JT_DDRC_CTRL JIO_32_RW | ||
44 | #define JN_DDRC_CTRL DDRC_CTRL | ||
45 | #define JI_DDRC_CTRL | ||
46 | |||
47 | #define REG_DDRC_TIMING1 jz_reg(DDRC_TIMING1) | ||
48 | #define JA_DDRC_TIMING1 (0xb34f0000 + 0x60) | ||
49 | #define JT_DDRC_TIMING1 JIO_32_RW | ||
50 | #define JN_DDRC_TIMING1 DDRC_TIMING1 | ||
51 | #define JI_DDRC_TIMING1 | ||
52 | |||
53 | #define REG_DDRC_TIMING2 jz_reg(DDRC_TIMING2) | ||
54 | #define JA_DDRC_TIMING2 (0xb34f0000 + 0x64) | ||
55 | #define JT_DDRC_TIMING2 JIO_32_RW | ||
56 | #define JN_DDRC_TIMING2 DDRC_TIMING2 | ||
57 | #define JI_DDRC_TIMING2 | ||
58 | |||
59 | #define REG_DDRC_TIMING3 jz_reg(DDRC_TIMING3) | ||
60 | #define JA_DDRC_TIMING3 (0xb34f0000 + 0x68) | ||
61 | #define JT_DDRC_TIMING3 JIO_32_RW | ||
62 | #define JN_DDRC_TIMING3 DDRC_TIMING3 | ||
63 | #define JI_DDRC_TIMING3 | ||
64 | |||
65 | #define REG_DDRC_TIMING4 jz_reg(DDRC_TIMING4) | ||
66 | #define JA_DDRC_TIMING4 (0xb34f0000 + 0x6c) | ||
67 | #define JT_DDRC_TIMING4 JIO_32_RW | ||
68 | #define JN_DDRC_TIMING4 DDRC_TIMING4 | ||
69 | #define JI_DDRC_TIMING4 | ||
70 | |||
71 | #define REG_DDRC_TIMING5 jz_reg(DDRC_TIMING5) | ||
72 | #define JA_DDRC_TIMING5 (0xb34f0000 + 0x70) | ||
73 | #define JT_DDRC_TIMING5 JIO_32_RW | ||
74 | #define JN_DDRC_TIMING5 DDRC_TIMING5 | ||
75 | #define JI_DDRC_TIMING5 | ||
76 | |||
77 | #define REG_DDRC_TIMING6 jz_reg(DDRC_TIMING6) | ||
78 | #define JA_DDRC_TIMING6 (0xb34f0000 + 0x74) | ||
79 | #define JT_DDRC_TIMING6 JIO_32_RW | ||
80 | #define JN_DDRC_TIMING6 DDRC_TIMING6 | ||
81 | #define JI_DDRC_TIMING6 | ||
82 | |||
83 | #define REG_DDRC_REFCNT jz_reg(DDRC_REFCNT) | ||
84 | #define JA_DDRC_REFCNT (0xb34f0000 + 0x18) | ||
85 | #define JT_DDRC_REFCNT JIO_32_RW | ||
86 | #define JN_DDRC_REFCNT DDRC_REFCNT | ||
87 | #define JI_DDRC_REFCNT | ||
88 | |||
89 | #define REG_DDRC_MMAP0 jz_reg(DDRC_MMAP0) | ||
90 | #define JA_DDRC_MMAP0 (0xb34f0000 + 0x24) | ||
91 | #define JT_DDRC_MMAP0 JIO_32_RW | ||
92 | #define JN_DDRC_MMAP0 DDRC_MMAP0 | ||
93 | #define JI_DDRC_MMAP0 | ||
94 | |||
95 | #define REG_DDRC_MMAP1 jz_reg(DDRC_MMAP1) | ||
96 | #define JA_DDRC_MMAP1 (0xb34f0000 + 0x28) | ||
97 | #define JT_DDRC_MMAP1 JIO_32_RW | ||
98 | #define JN_DDRC_MMAP1 DDRC_MMAP1 | ||
99 | #define JI_DDRC_MMAP1 | ||
100 | |||
101 | #define REG_DDRC_DLP jz_reg(DDRC_DLP) | ||
102 | #define JA_DDRC_DLP (0xb34f0000 + 0xbc) | ||
103 | #define JT_DDRC_DLP JIO_32_RW | ||
104 | #define JN_DDRC_DLP DDRC_DLP | ||
105 | #define JI_DDRC_DLP | ||
106 | |||
107 | #define REG_DDRC_REMAP1 jz_reg(DDRC_REMAP1) | ||
108 | #define JA_DDRC_REMAP1 (0xb34f0000 + 0x9c) | ||
109 | #define JT_DDRC_REMAP1 JIO_32_RW | ||
110 | #define JN_DDRC_REMAP1 DDRC_REMAP1 | ||
111 | #define JI_DDRC_REMAP1 | ||
112 | |||
113 | #define REG_DDRC_REMAP2 jz_reg(DDRC_REMAP2) | ||
114 | #define JA_DDRC_REMAP2 (0xb34f0000 + 0xa0) | ||
115 | #define JT_DDRC_REMAP2 JIO_32_RW | ||
116 | #define JN_DDRC_REMAP2 DDRC_REMAP2 | ||
117 | #define JI_DDRC_REMAP2 | ||
118 | |||
119 | #define REG_DDRC_REMAP3 jz_reg(DDRC_REMAP3) | ||
120 | #define JA_DDRC_REMAP3 (0xb34f0000 + 0xa4) | ||
121 | #define JT_DDRC_REMAP3 JIO_32_RW | ||
122 | #define JN_DDRC_REMAP3 DDRC_REMAP3 | ||
123 | #define JI_DDRC_REMAP3 | ||
124 | |||
125 | #define REG_DDRC_REMAP4 jz_reg(DDRC_REMAP4) | ||
126 | #define JA_DDRC_REMAP4 (0xb34f0000 + 0xa8) | ||
127 | #define JT_DDRC_REMAP4 JIO_32_RW | ||
128 | #define JN_DDRC_REMAP4 DDRC_REMAP4 | ||
129 | #define JI_DDRC_REMAP4 | ||
130 | |||
131 | #define REG_DDRC_REMAP5 jz_reg(DDRC_REMAP5) | ||
132 | #define JA_DDRC_REMAP5 (0xb34f0000 + 0xac) | ||
133 | #define JT_DDRC_REMAP5 JIO_32_RW | ||
134 | #define JN_DDRC_REMAP5 DDRC_REMAP5 | ||
135 | #define JI_DDRC_REMAP5 | ||
136 | |||
137 | #define REG_DDRC_AUTOSR_CNT jz_reg(DDRC_AUTOSR_CNT) | ||
138 | #define JA_DDRC_AUTOSR_CNT (0xb34f0000 + 0x308) | ||
139 | #define JT_DDRC_AUTOSR_CNT JIO_32_RW | ||
140 | #define JN_DDRC_AUTOSR_CNT DDRC_AUTOSR_CNT | ||
141 | #define JI_DDRC_AUTOSR_CNT | ||
142 | |||
143 | #define REG_DDRC_AUTOSR_EN jz_reg(DDRC_AUTOSR_EN) | ||
144 | #define JA_DDRC_AUTOSR_EN (0xb34f0000 + 0x304) | ||
145 | #define JT_DDRC_AUTOSR_EN JIO_32_RW | ||
146 | #define JN_DDRC_AUTOSR_EN DDRC_AUTOSR_EN | ||
147 | #define JI_DDRC_AUTOSR_EN | ||
148 | |||
149 | #endif /* __HEADERGEN_DDRC_H__*/ | ||