x1000: spl: remove dual boot support code

Removes the SPL's dual boot support code, and removes the dual
boot selection code on the M3K and Q1 since they can now do it
from the main bootloader.

Change-Id: Ie1b27e98c6ed4b3e37db86cfb485d6f3a6c5b25e

1 files changed, 0 insertions, 86 deletions

diff --git a/firmware/target/mips/ingenic_x1000/spl-x1000.c b/firmware/target/mips/ingenic_x1000/spl-x1000.c
index ac3a17f69f..1abbdcd7a4 100644
--- a/firmware/target/mips/ingenic_x1000/spl-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/spl-x1000.c
@@ -55,92 +55,6 @@ void* spl_alloc(size_t count)
     return heap;
 }
 
-/* Used by:
- * - FiiO M3K
- * - Shanling Q1
- *
- * Amend it and add #ifdefs for other targets if needed.
- */
-void spl_dualboot_init_clocktree(void)
-{
-    /* Make sure these are gated to match the OF behavior. */
-    jz_writef(CPM_CLKGR, PCM(1), MAC(1), LCD(1), MSC0(1), MSC1(1), OTG(1), CIM(1));
-
-    /* Set clock sources, and make sure every clock starts out stopped */
-    jz_writef(CPM_I2SCDR, CS_V(EXCLK));
-    jz_writef(CPM_PCMCDR, CS_V(EXCLK));
-
-    jz_writef(CPM_MACCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe));
-    while(jz_readf(CPM_MACCDR, BUSY));
-
-    jz_writef(CPM_LPCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe));
-    while(jz_readf(CPM_LPCDR, BUSY));
-
-    jz_writef(CPM_MSC0CDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe));
-    while(jz_readf(CPM_MSC0CDR, BUSY));
-
-    jz_writef(CPM_MSC1CDR, CE(1), STOP(1), CLKDIV(0xfe));
-    while(jz_readf(CPM_MSC1CDR, BUSY));
-
-    jz_writef(CPM_CIMCDR, CLKSRC_V(MPLL), CE(1), STOP(1), CLKDIV(0xfe));
-    while(jz_readf(CPM_CIMCDR, BUSY));
-
-    jz_writef(CPM_USBCDR, CLKSRC_V(EXCLK), CE(1), STOP(1));
-    while(jz_readf(CPM_USBCDR, BUSY));
-}
-
-void spl_dualboot_init_uart2(void)
-{
-    /* Ungate the clock and select UART2 device function */
-    jz_writef(CPM_CLKGR, UART2(0));
-    gpioz_configure(GPIO_C, 3 << 30, GPIOF_DEVICE(1));
-
-    /* Disable all interrupts */
-    jz_write(UART_UIER(2), 0);
-
-    /* FIFO configuration */
-    jz_overwritef(UART_UFCR(2),
-                  RDTR(3), /* FIFO trigger level = 60? */
-                  UME(0),  /* UART module disable */
-                  DME(1),  /* DMA mode enable? */
-                  TFRT(1), /* transmit FIFO reset */
-                  RFRT(1), /* receive FIFO reset */
-                  FME(1)); /* FIFO mode enable */
-
-    /* IR mode configuration */
-    jz_overwritef(UART_ISR(2),
-                  RDPL(1),      /* Zero is negative pulse for receive */
-                  TDPL(1),      /* ... and for transmit */
-                  XMODE(1),     /* Pulse width 1.6us */
-                  RCVEIR(0),    /* Disable IR for recieve */
-                  XMITIR(0));   /* ... and for transmit */
-
-    /* Line configuration */
-    jz_overwritef(UART_ULCR(2), DLAB(0),
-                  WLS_V(8BITS),         /* 8 bit words */
-                  SBLS_V(1_STOP_BIT),   /* 1 stop bit */
-                  PARE(0),              /* no parity */
-                  SBK(0));              /* don't set break */
-
-    /* Set the baud rate... not too sure how this works. (Docs unclear!) */
-    const unsigned divisor = 0x0004;
-    jz_writef(UART_ULCR(2), DLAB(1));
-    jz_write(UART_UDLHR(2), (divisor >> 8) & 0xff);
-    jz_write(UART_UDLLR(2), divisor & 0xff);
-    jz_write(UART_UMR(2), 16);
-    jz_write(UART_UACR(2), 0);
-    jz_writef(UART_ULCR(2), DLAB(0));
-
-    /* Enable UART */
-    jz_overwritef(UART_UFCR(2),
-                  RDTR(0),  /* FIFO trigger level = 1 */
-                  DME(0),   /* DMA mode disable */
-                  UME(1),   /* UART module enable */
-                  TFRT(1),  /* transmit FIFO reset */
-                  RFRT(1),  /* receive FIFO reset */
-                  FME(1));  /* FIFO mode enable */
-}
-
 static void init_ost(void)
 {
     /* NOTE: the prescaler needs to be the same as in system-x1000.c */