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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-11 13:28:43 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-12 10:35:20 +0000 |
commit | 3f26fcf34001197ed267fa1ad549095aae49c88e (patch) | |
tree | c81ab3298a349d1156e905d467492b603236f74d /firmware/target/mips/ingenic_x1000/spl-start.S | |
parent | cc22df198d0ccb64dfdfe0c2f247f7d86b7fd750 (diff) | |
download | rockbox-3f26fcf34001197ed267fa1ad549095aae49c88e.tar.gz rockbox-3f26fcf34001197ed267fa1ad549095aae49c88e.zip |
FiiO M3K: New bootloaderbootloader_fiiom3k_v1
SPL and UCL-compressed bootloader are now packed into one output,
bootloader.m3k, eliminating the separate SPL build phase.
The Rockbox bootloader now has a recovery menu, accessible by
holding VOL+ when booting, that lets you back up, restore, and
update the bootloader from the device.
Change-Id: I642c6e5fb83587a013ab2fbfd1adab439561ced2
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/spl-start.S')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/spl-start.S | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/spl-start.S b/firmware/target/mips/ingenic_x1000/spl-start.S new file mode 100644 index 0000000000..58346fe750 --- /dev/null +++ b/firmware/target/mips/ingenic_x1000/spl-start.S | |||
@@ -0,0 +1,97 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2021 Aidan MacDonald | ||
11 | * | ||
12 | * This program is free software; you can redistribute it and/or | ||
13 | * modify it under the terms of the GNU General Public License | ||
14 | * as published by the Free Software Foundation; either version 2 | ||
15 | * of the License, or (at your option) any later version. | ||
16 | * | ||
17 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
18 | * KIND, either express or implied. | ||
19 | * | ||
20 | ****************************************************************************/ | ||
21 | |||
22 | #include "config.h" | ||
23 | #include "mips.h" | ||
24 | |||
25 | .text | ||
26 | .extern spl_main | ||
27 | .global _spl_start | ||
28 | |||
29 | .set push | ||
30 | .set mips32 | ||
31 | .set noreorder | ||
32 | .set noat | ||
33 | |||
34 | .section .init.spl | ||
35 | |||
36 | _spl_start: | ||
37 | /* Clear data watchpoint */ | ||
38 | mtc0 zero, C0_WATCHLO | ||
39 | mtc0 zero, C0_WATCHHI | ||
40 | |||
41 | /* Set BEV, ERL, mask interrupts */ | ||
42 | li v0, 0x40fc04 | ||
43 | mtc0 v0, C0_Status | ||
44 | |||
45 | /* Set Cause_IV to 1 (use special interrupt vector) */ | ||
46 | li v0, M_CauseIV | ||
47 | mtc0 v0, C0_Cause | ||
48 | |||
49 | /* Set CPU_MODE and BUS_MODE to 1 in CPM_OPCR (Ingenic does this) */ | ||
50 | lui v0, 0xb000 | ||
51 | lw v1, 0x24(v0) | ||
52 | ori v1, v1, 0x22 | ||
53 | sw v1, 0x24(v0) | ||
54 | |||
55 | /* Enable kseg0 cacheability */ | ||
56 | li v0, 3 | ||
57 | mtc0 v0, C0_Config | ||
58 | nop | ||
59 | |||
60 | /* According to ingenic: "enable idx-store-data cache insn" */ | ||
61 | li v0, 0x20000000 | ||
62 | mtc0 v0, C0_ErrCtl | ||
63 | |||
64 | /* Cache init */ | ||
65 | li v0, 0x80000000 | ||
66 | ori v1, v0, 0x4000 | ||
67 | mtc0 zero, C0_TAGLO | ||
68 | mtc0 zero, C0_TAGHI | ||
69 | _cache_loop: | ||
70 | cache ICIndexStTag, 0(v0) | ||
71 | cache DCIndexStTag, 0(v0) | ||
72 | addiu v0, v0, 32 | ||
73 | bne v0, v1, _cache_loop | ||
74 | nop | ||
75 | |||
76 | /* Invalidate BTB */ | ||
77 | mfc0 v0, C0_Config, 7 | ||
78 | nop | ||
79 | ori v0, v0, 2 | ||
80 | mtc0 v0, C0_Config, 7 | ||
81 | nop | ||
82 | |||
83 | /* Clear the BSS segment (needed to zero-initialize C static values) */ | ||
84 | la t0, _bssbegin | ||
85 | la t1, _bssend | ||
86 | beq t0, t1, _bss_done | ||
87 | _bss_loop: | ||
88 | addiu t0, 4 | ||
89 | bne t0, t1, _bss_loop | ||
90 | sw zero, -4(t0) | ||
91 | _bss_done: | ||
92 | |||
93 | /* Jump to C code */ | ||
94 | j spl_main | ||
95 | nop | ||
96 | |||
97 | .set pop | ||