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author | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-11 13:28:43 +0100 |
---|---|---|
committer | Aidan MacDonald <amachronic@protonmail.com> | 2021-05-12 10:35:20 +0000 |
commit | 3f26fcf34001197ed267fa1ad549095aae49c88e (patch) | |
tree | c81ab3298a349d1156e905d467492b603236f74d /firmware/target/mips/ingenic_x1000/nand-x1000.h | |
parent | cc22df198d0ccb64dfdfe0c2f247f7d86b7fd750 (diff) | |
download | rockbox-3f26fcf34001197ed267fa1ad549095aae49c88e.tar.gz rockbox-3f26fcf34001197ed267fa1ad549095aae49c88e.zip |
FiiO M3K: New bootloaderbootloader_fiiom3k_v1
SPL and UCL-compressed bootloader are now packed into one output,
bootloader.m3k, eliminating the separate SPL build phase.
The Rockbox bootloader now has a recovery menu, accessible by
holding VOL+ when booting, that lets you back up, restore, and
update the bootloader from the device.
Change-Id: I642c6e5fb83587a013ab2fbfd1adab439561ced2
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.h')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.h b/firmware/target/mips/ingenic_x1000/nand-x1000.h index 6c415b1170..f5db0bbfa5 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.h +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.h | |||
@@ -36,7 +36,14 @@ | |||
36 | #include <stdint.h> | 36 | #include <stdint.h> |
37 | #include <stdbool.h> | 37 | #include <stdbool.h> |
38 | #include <stddef.h> | 38 | #include <stddef.h> |
39 | #include "nand-x1000-err.h" | 39 | |
40 | /* Error codes which can be returned by the NAND API */ | ||
41 | #define NAND_SUCCESS 0 | ||
42 | #define NAND_ERR_UNKNOWN_CHIP (-1) | ||
43 | #define NAND_ERR_UNALIGNED (-2) | ||
44 | #define NAND_ERR_WRITE_PROTECT (-3) | ||
45 | #define NAND_ERR_CONTROLLER (-4) | ||
46 | #define NAND_ERR_COMMAND (-5) | ||
40 | 47 | ||
41 | /* Chip supports quad I/O for page read/write */ | 48 | /* Chip supports quad I/O for page read/write */ |
42 | #define NANDCHIP_FLAG_QUAD 0x01 | 49 | #define NANDCHIP_FLAG_QUAD 0x01 |