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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-06-07 19:37:11 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-09-17 10:14:26 -0400 |
commit | e64b0e81ad76ef057b7a3c79ac8a810c1b73faaf (patch) | |
tree | b3be811c48b7903db5b26cb0b7e14bf3e796fe15 /firmware/target/mips/ingenic_x1000/nand-x1000.c | |
parent | 17443de2214f7bfe77e1ebc11c268adaa15ae856 (diff) | |
download | rockbox-e64b0e81ad76ef057b7a3c79ac8a810c1b73faaf.tar.gz rockbox-e64b0e81ad76ef057b7a3c79ac8a810c1b73faaf.zip |
x1000: add support for the W25N01GVxx NAND flash
This chip is apparently used in some Surfans F20 units, and has
the same geometry as the ATO25D1GA. It has an on-die ECC engine.
Change-Id: I4d37a2455620ce43cec0a9bcbb32c776d1a8eba1
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 6255597165..c78f990f5f 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -25,6 +25,8 @@ | |||
25 | #include "logf.h" | 25 | #include "logf.h" |
26 | #include <string.h> | 26 | #include <string.h> |
27 | 27 | ||
28 | static void winbond_setup_chip(struct nand_drv* drv); | ||
29 | |||
28 | static const struct nand_chip chip_ato25d1ga = { | 30 | static const struct nand_chip chip_ato25d1ga = { |
29 | .log2_ppb = 6, /* 64 pages */ | 31 | .log2_ppb = 6, /* 64 pages */ |
30 | .page_size = 2048, | 32 | .page_size = 2048, |
@@ -46,9 +48,32 @@ static const struct nand_chip chip_ato25d1ga = { | |||
46 | .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4, | 48 | .cmd_program_load = NANDCMD_PROGRAM_LOAD_x4, |
47 | }; | 49 | }; |
48 | 50 | ||
51 | static const struct nand_chip chip_w25n01gvxx = { | ||
52 | .log2_ppb = 6, /* 64 pages */ | ||
53 | .page_size = 2048, | ||
54 | .oob_size = 64, | ||
55 | .nr_blocks = 1024, | ||
56 | .bbm_pos = 2048, | ||
57 | .clock_freq = 150000000, | ||
58 | .dev_conf = jz_orf(SFC_DEV_CONF, | ||
59 | CE_DL(1), HOLD_DL(1), WP_DL(1), | ||
60 | CPHA(0), CPOL(0), | ||
61 | TSH(11), TSETUP(0), THOLD(0), | ||
62 | STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), | ||
63 | SMP_DELAY(1)), | ||
64 | .flags = NAND_CHIPFLAG_ON_DIE_ECC, | ||
65 | /* TODO: quad mode? */ | ||
66 | .cmd_page_read = NANDCMD_PAGE_READ, | ||
67 | .cmd_program_execute = NANDCMD_PROGRAM_EXECUTE, | ||
68 | .cmd_block_erase = NANDCMD_BLOCK_ERASE, | ||
69 | .cmd_read_cache = NANDCMD_READ_CACHE_SLOW, | ||
70 | .cmd_program_load = NANDCMD_PROGRAM_LOAD, | ||
71 | .setup_chip = winbond_setup_chip, | ||
72 | }; | ||
49 | 73 | ||
50 | const struct nand_chip_id supported_nand_chips[] = { | 74 | const struct nand_chip_id supported_nand_chips[] = { |
51 | NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12), | 75 | NAND_CHIP_ID(&chip_ato25d1ga, NAND_READID_ADDR, 0x9b, 0x12), |
76 | NAND_CHIP_ID(&chip_w25n01gvxx, NAND_READID_ADDR, 0xef, 0xaa, 0x21), | ||
52 | }; | 77 | }; |
53 | 78 | ||
54 | const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips); | 79 | const size_t nr_supported_nand_chips = ARRAYLEN(supported_nand_chips); |
@@ -127,6 +152,12 @@ static void setup_chip_data(struct nand_drv* drv) | |||
127 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; | 152 | drv->fpage_size = drv->chip->page_size + drv->chip->oob_size; |
128 | } | 153 | } |
129 | 154 | ||
155 | static void winbond_setup_chip(struct nand_drv* drv) | ||
156 | { | ||
157 | /* Ensure we are in buffered read mode. */ | ||
158 | nand_upd_reg(drv, FREG_CFG, FREG_CFG_WINBOND_BUF, FREG_CFG_WINBOND_BUF); | ||
159 | } | ||
160 | |||
130 | static void setup_chip_registers(struct nand_drv* drv) | 161 | static void setup_chip_registers(struct nand_drv* drv) |
131 | { | 162 | { |
132 | /* Set chip registers to enter normal operation */ | 163 | /* Set chip registers to enter normal operation */ |