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author | Aidan MacDonald <amachronic@protonmail.com> | 2022-05-30 14:02:13 +0100 |
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committer | Aidan MacDonald <amachronic@protonmail.com> | 2022-05-30 14:02:13 +0100 |
commit | e05aa27124461ccf85109ae8d249924895f07a3e (patch) | |
tree | 8e2db36ea4b53641a9dc907208a43ee909cf3bb3 /firmware/target/mips/ingenic_x1000/nand-x1000.c | |
parent | 1d392613389d36e41edc56b9dff166c8b0172d0a (diff) | |
download | rockbox-e05aa27124461ccf85109ae8d249924895f07a3e.tar.gz rockbox-e05aa27124461ccf85109ae8d249924895f07a3e.zip |
x1000: move NAND commands to header file
Change-Id: Ic95b80494a101f7b349e115d82e9dfe3a64b643f
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/nand-x1000.c')
-rw-r--r-- | firmware/target/mips/ingenic_x1000/nand-x1000.c | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/firmware/target/mips/ingenic_x1000/nand-x1000.c b/firmware/target/mips/ingenic_x1000/nand-x1000.c index 5838b21b39..18d548ba8c 100644 --- a/firmware/target/mips/ingenic_x1000/nand-x1000.c +++ b/firmware/target/mips/ingenic_x1000/nand-x1000.c | |||
@@ -24,39 +24,6 @@ | |||
24 | #include "system.h" | 24 | #include "system.h" |
25 | #include <string.h> | 25 | #include <string.h> |
26 | 26 | ||
27 | /* cmd mode a d phase format has data */ | ||
28 | #define NANDCMD_RESET SFC_CMD(0xff, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) | ||
29 | #define NANDCMD_READID(x,y) SFC_CMD(0x9f, SFC_TMODE_1_1_1, x, y, SFC_PFMT_ADDR_FIRST, 1) | ||
30 | #define NANDCMD_WR_EN SFC_CMD(0x06, SFC_TMODE_1_1_1, 0, 0, SFC_PFMT_ADDR_FIRST, 0) | ||
31 | #define NANDCMD_GET_FEATURE SFC_CMD(0x0f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) | ||
32 | #define NANDCMD_SET_FEATURE SFC_CMD(0x1f, SFC_TMODE_1_1_1, 1, 0, SFC_PFMT_ADDR_FIRST, 1) | ||
33 | #define NANDCMD_PAGE_READ(x) SFC_CMD(0x13, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | ||
34 | #define NANDCMD_READ_CACHE(x) SFC_CMD(0x0b, SFC_TMODE_1_1_1, x, 8, SFC_PFMT_ADDR_FIRST, 1) | ||
35 | #define NANDCMD_READ_CACHE_x4(x) SFC_CMD(0x6b, SFC_TMODE_1_1_4, x, 8, SFC_PFMT_ADDR_FIRST, 1) | ||
36 | #define NANDCMD_PROGRAM_LOAD(x) SFC_CMD(0x02, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 1) | ||
37 | #define NANDCMD_PROGRAM_LOAD_x4(x) SFC_CMD(0x32, SFC_TMODE_1_1_4, x, 0, SFC_PFMT_ADDR_FIRST, 1) | ||
38 | #define NANDCMD_PROGRAM_EXECUTE(x) SFC_CMD(0x10, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | ||
39 | #define NANDCMD_BLOCK_ERASE(x) SFC_CMD(0xd8, SFC_TMODE_1_1_1, x, 0, SFC_PFMT_ADDR_FIRST, 0) | ||
40 | |||
41 | /* Feature registers are found in linux/mtd/spinand.h, | ||
42 | * apparently these are pretty standardized */ | ||
43 | #define FREG_PROT 0xa0 | ||
44 | #define FREG_PROT_UNLOCK 0x00 | ||
45 | |||
46 | #define FREG_CFG 0xb0 | ||
47 | #define FREG_CFG_OTP_ENABLE (1 << 6) | ||
48 | #define FREG_CFG_ECC_ENABLE (1 << 4) | ||
49 | #define FREG_CFG_QUAD_ENABLE (1 << 0) | ||
50 | |||
51 | #define FREG_STATUS 0xc0 | ||
52 | #define FREG_STATUS_BUSY (1 << 0) | ||
53 | #define FREG_STATUS_EFAIL (1 << 2) | ||
54 | #define FREG_STATUS_PFAIL (1 << 3) | ||
55 | #define FREG_STATUS_ECC_MASK (3 << 4) | ||
56 | #define FREG_STATUS_ECC_NO_FLIPS (0 << 4) | ||
57 | #define FREG_STATUS_ECC_HAS_FLIPS (1 << 4) | ||
58 | #define FREG_STATUS_ECC_UNCOR_ERR (2 << 4) | ||
59 | |||
60 | const nand_chip supported_nand_chips[] = { | 27 | const nand_chip supported_nand_chips[] = { |
61 | #if defined(FIIO_M3K) || defined(SHANLING_Q1) || defined(EROS_QN) | 28 | #if defined(FIIO_M3K) || defined(SHANLING_Q1) || defined(EROS_QN) |
62 | { | 29 | { |