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authorAidan MacDonald <amachronic@protonmail.com>2021-04-28 02:32:47 +0100
committerAidan MacDonald <amachronic@protonmail.com>2021-04-28 20:04:10 +0100
commit16a1993cadfb3da9df25d5436ebf355ed31cc5b1 (patch)
tree2a0097ff1683471cb2fc156f248c8043bb6d2116 /firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
parent423fcf951a12178c6a4060a72a00aa722330aca1 (diff)
downloadrockbox-16a1993cadfb3da9df25d5436ebf355ed31cc5b1.tar.gz
rockbox-16a1993cadfb3da9df25d5436ebf355ed31cc5b1.zip
x1000: Remove some #ifdef SPL in the sfc/nand code
Change-Id: I554d590bfa700e521a74b5216e09f9673902d676
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h')
-rw-r--r--firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
index 26a8b840c9..1238d7e452 100644
--- a/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
+++ b/firmware/target/mips/ingenic_x1000/fiiom3k/nand-target.h
@@ -25,11 +25,6 @@
25/* The max page size (main + spare) of all NAND chips used by this target */ 25/* The max page size (main + spare) of all NAND chips used by this target */
26#define NAND_MAX_PAGE_SIZE (2048 + 64) 26#define NAND_MAX_PAGE_SIZE (2048 + 64)
27 27
28/* The clock source to use for the SFC controller. Note the SPL has special
29 * handling which ignores this choice, so it only applies to bootloader & app.
30 */
31#define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A
32
33/* The clock speed to use for the SFC controller during chip identification */ 28/* The clock speed to use for the SFC controller during chip identification */
34#define NAND_INIT_CLOCK_SPEED 150000000 29#define NAND_INIT_CLOCK_SPEED 150000000
35 30