summaryrefslogtreecommitdiff
path: root/firmware/target/mips/ingenic_x1000/boot-x1000.c
diff options
context:
space:
mode:
authorAidan MacDonald <amachronic@protonmail.com>2022-03-16 15:35:39 +0000
committerAidan MacDonald <amachronic@protonmail.com>2022-03-24 23:40:07 +0000
commit44fbb1a59363a464d637d93656e9b29858451550 (patch)
tree759967e10b73d52d52be3ca156b43fa4db979ab1 /firmware/target/mips/ingenic_x1000/boot-x1000.c
parent90cb0b0ae541303b3efb5ddbdc2ff8adab26cb49 (diff)
downloadrockbox-44fbb1a59363a464d637d93656e9b29858451550.tar.gz
rockbox-44fbb1a59363a464d637d93656e9b29858451550.zip
x1000: bootloader: add LCD dualboot cleanup for the M3K
Disable LCD interrupts before booting the OF - the OF kernel hangs at boot if they are enabled. Change-Id: I4f119818d0243953cdd620e17d9509b4fb16cc28
Diffstat (limited to 'firmware/target/mips/ingenic_x1000/boot-x1000.c')
-rw-r--r--firmware/target/mips/ingenic_x1000/boot-x1000.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/firmware/target/mips/ingenic_x1000/boot-x1000.c b/firmware/target/mips/ingenic_x1000/boot-x1000.c
index feb67994b7..aa97bfcd85 100644
--- a/firmware/target/mips/ingenic_x1000/boot-x1000.c
+++ b/firmware/target/mips/ingenic_x1000/boot-x1000.c
@@ -145,13 +145,11 @@ void rolo_restart(const unsigned char* source, unsigned char* dest, int length)
145 145
146void x1000_dualboot_cleanup(void) 146void x1000_dualboot_cleanup(void)
147{ 147{
148#ifdef SHANLING_Q1 148 /* - disable all LCD interrupts since the M3K can't cope with them
149 /* hack for the Q1 since OF kernels don't reset this bit, 149 * - disable BEDN bit since it creates garbled graphics on the Q1 */
150 * leading to garbled graphics. */ 150 jz_writef(CPM_CLKGR, LCD(0));
151 if(!jz_readf(CPM_CLKGR, LCD)) { 151 jz_writef(LCD_CTRL, BEDN(0), EOFM(0), SOFM(0), IFUM(0), QDM(0));
152 jz_writef(LCD_CTRL, BEDN(0)); 152 jz_writef(CPM_CLKGR, LCD(1));
153 }
154#endif
155 153
156 /* clear USB PHY voodoo bits, not all kernels use them */ 154 /* clear USB PHY voodoo bits, not all kernels use them */
157 jz_writef(CPM_OPCR, GATE_USBPHY_CLK(0)); 155 jz_writef(CPM_OPCR, GATE_USBPHY_CLK(0));