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authorMaurus Cuelenaere <mcuelenaere@gmail.com>2009-06-18 18:16:15 +0000
committerMaurus Cuelenaere <mcuelenaere@gmail.com>2009-06-18 18:16:15 +0000
commit2fb6396f5a73e52d059f8472a8dceba59ce31250 (patch)
tree5f0da6964bc5f4582b88d2f16a3d2eb8626ee628 /firmware/target/mips/ingenic_jz47xx
parent0181bc42c942797b1e215e6f7861aa760207b8db (diff)
downloadrockbox-2fb6396f5a73e52d059f8472a8dceba59ce31250.tar.gz
rockbox-2fb6396f5a73e52d059f8472a8dceba59ce31250.zip
Ingenic Jz4740: enable IRAM (only core, without ibss)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21331 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/app.lds32
-rw-r--r--firmware/target/mips/ingenic_jz47xx/crt0.S12
2 files changed, 12 insertions, 32 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/app.lds b/firmware/target/mips/ingenic_jz47xx/app.lds
index 61bfd2e613..e8c9ebf65b 100644
--- a/firmware/target/mips/ingenic_jz47xx/app.lds
+++ b/firmware/target/mips/ingenic_jz47xx/app.lds
@@ -16,7 +16,7 @@ STARTUP(target/mips/ingenic_jz47xx/crt0.o)
16 16
17#define DRAMORIG 0x80004000 17#define DRAMORIG 0x80004000
18#define IRAMORIG 0x80000000 18#define IRAMORIG 0x80000000
19#define IRAMSIZE (16K-0x220) 19#define IRAMSIZE 16K
20 20
21/* End of the audio buffer, where the codec buffer starts */ 21/* End of the audio buffer, where the codec buffer starts */
22#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE) 22#define ENDAUDIOADDR (DRAMORIG + DRAMSIZE)
@@ -41,14 +41,14 @@ SECTIONS
41 *(.init.text); 41 *(.init.text);
42 *(.text*); 42 *(.text*);
43 } > DRAM 43 } > DRAM
44 44
45 . = ALIGN(4); 45 . = ALIGN(4);
46 46
47 .rodata : 47 .rodata :
48 { 48 {
49 *(.rodata*); 49 *(.rodata*);
50 } > DRAM 50 } > DRAM
51 51
52 . = ALIGN(4); 52 . = ALIGN(4);
53 53
54 .data : 54 .data :
@@ -57,9 +57,9 @@ SECTIONS
57 *(.sdata*); 57 *(.sdata*);
58 *(.rel.dyn); 58 *(.rel.dyn);
59 } > DRAM 59 } > DRAM
60 60
61 . = ALIGN(4); 61 . = ALIGN(4);
62 62
63 /* Set the load address of .iram at the same address as .bss 63 /* Set the load address of .iram at the same address as .bss
64 * so RAM won't be wasted as .iram in the end will get copied 64 * so RAM won't be wasted as .iram in the end will get copied
65 * to IRAM. */ 65 * to IRAM. */
@@ -74,7 +74,7 @@ SECTIONS
74 . = 0x200; 74 . = 0x200;
75 *(.vectors.4); 75 *(.vectors.4);
76 *(.vectors); 76 *(.vectors);
77 77
78 *(.icode); 78 *(.icode);
79 *(.irodata); 79 *(.irodata);
80 *(.idata); 80 *(.idata);
@@ -83,9 +83,9 @@ SECTIONS
83 _iramend = .; 83 _iramend = .;
84 } > IRAM 84 } > IRAM
85 _iramcopy = LOADADDR(.iram); 85 _iramcopy = LOADADDR(.iram);
86 86
87 . = ALIGN(4); 87 . = ALIGN(4);
88 88
89 .stack (NOLOAD): 89 .stack (NOLOAD):
90 { 90 {
91 *(.stack); 91 *(.stack);
@@ -93,28 +93,20 @@ SECTIONS
93 . += 0x2000; 93 . += 0x2000;
94 stackend = .; 94 stackend = .;
95 } > IRAM 95 } > IRAM
96
97 . = ALIGN(4);
98 96
99 .bss (NOLOAD): 97 .bss (NOLOAD):
100 { 98 {
101 _edata = .; 99 _edata = .;
102 *(.sbss*); 100 *(.sbss*);
103 *(.bss*); 101 *(.bss*);
102 *(.ibss*); /* Don't put this in IRAM as there's not enough space */
104 *(COMMON); 103 *(COMMON);
105 *(.scommon*); 104 *(.scommon*);
106 _end = .; 105 _end = .;
107 } > DRAM 106 } > DRAM
108 107
109 . = ALIGN(4); 108 . = ALIGN(4);
110 109
111 .ibss (NOLOAD) :
112 {
113 _iedata = .;
114 *(.ibss*);
115 _iend = .;
116 } > IRAM
117
118 .audiobuf ALIGN(4) : 110 .audiobuf ALIGN(4) :
119 { 111 {
120 audiobuffer = .; 112 audiobuffer = .;
@@ -134,7 +126,7 @@ SECTIONS
134 { 126 {
135 pluginbuf = .; 127 pluginbuf = .;
136 } 128 }
137 129
138 /DISCARD/ : 130 /DISCARD/ :
139 { 131 {
140 *(.eh_frame); 132 *(.eh_frame);
diff --git a/firmware/target/mips/ingenic_jz47xx/crt0.S b/firmware/target/mips/ingenic_jz47xx/crt0.S
index 783773cf0c..111244b173 100644
--- a/firmware/target/mips/ingenic_jz47xx/crt0.S
+++ b/firmware/target/mips/ingenic_jz47xx/crt0.S
@@ -147,18 +147,6 @@ _bss_loop:
147 sw zero, 0(t0) 147 sw zero, 0(t0)
148 bne t0, t1, _bss_loop 148 bne t0, t1, _bss_loop
149 addiu t0, 4 149 addiu t0, 4
150
151 /*
152 ----------------------------------------------------
153 Clear IBSS section
154 ----------------------------------------------------
155 */
156 la t0, _iedata
157 la t1, _iend
158_ibss_loop:
159 sw zero, 0(t0)
160 bne t0, t1, _ibss_loop
161 addiu t0, 4
162 150
163 /* 151 /*
164 ---------------------------------------------------- 152 ----------------------------------------------------