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authorSolomon Peachy <pizza@shaftnet.org>2020-09-02 08:25:43 -0400
committerSolomon Peachy <pizza@shaftnet.org>2020-09-02 08:29:04 -0400
commitbb6fc21244032fd763159d02639e91390712dec2 (patch)
treef8173b2553ef878dbce03192d441fe2b7ac6cfce /firmware/target/mips/ingenic_jz47xx/system-target.h
parent963e979e6c1abeb81d1f4e1a2cca92ed220f0a67 (diff)
downloadrockbox-bb6fc21244032fd763159d02639e91390712dec2.tar.gz
rockbox-bb6fc21244032fd763159d02639e91390712dec2.zip
mips: use .set push/pop in asm code
Change-Id: I3e7bc7ffb8d6d0c5d18a6ab38b1a270559a62fb9
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-target.h')
-rw-r--r--firmware/target/mips/ingenic_jz47xx/system-target.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index d8c395cef2..30c1668bf7 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -123,7 +123,10 @@ static inline void core_sleep(void)
123#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B 123#if CONFIG_CPU == JZ4732 || CONFIG_CPU == JZ4760B
124 __cpm_idle_mode(); 124 __cpm_idle_mode();
125#endif 125#endif
126 asm volatile(".set mips32r2 \n" 126 asm volatile(
127 ".set push \n"
128 ".set mips32r2 \n"
129 ".set noreorder \n"
127 "mfc0 $8, $12 \n" /* mfc t0, $12 */ 130 "mfc0 $8, $12 \n" /* mfc t0, $12 */
128 "move $9, $8 \n" /* move t1, t0 */ 131 "move $9, $8 \n" /* move t1, t0 */
129 "la $10, 0x8000000 \n" /* la t2, 0x8000000 */ 132 "la $10, 0x8000000 \n" /* la t2, 0x8000000 */
@@ -131,7 +134,7 @@ static inline void core_sleep(void)
131 "mtc0 $8, $12 \n" /* mtc t0, $12 */ 134 "mtc0 $8, $12 \n" /* mtc t0, $12 */
132 "wait \n" 135 "wait \n"
133 "mtc0 $9, $12 \n" /* mtc t1, $12 */ 136 "mtc0 $9, $12 \n" /* mtc t1, $12 */
134 ".set mips0 \n" 137 ".set pop \n"
135 ::: "t0", "t1", "t2" 138 ::: "t0", "t1", "t2"
136 ); 139 );
137 enable_irq(); 140 enable_irq();