Fix MIPS cache operations and enable HAVE_CPU_CACHE_ALIGN on MIPS

- The range-based cache operations on MIPS were broken and only worked
  properly when BOTH the address and size were multiples of the cache
  line size. If this was not the case, the last cache line of the range
  would not be touched!

  Fix is to align start/end pointers to cache lines before iterating.

- To my knowledge all MIPS processors have a cache, so I enabled
  HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
  the CACHEALIGN_UP/DOWN macros.

- Make jz4760/system-target.h define its cache line size properly.

Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7

1 files changed, 1 insertions, 1 deletions

diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 9dc1a5c8c8..862ec403d2 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -29,7 +29,7 @@
 #include "mipsregs.h"
 
 #define CACHE_SIZE       16*1024
-#define CACHE_LINE_SIZE  32
+#define CACHEALIGN_BITS  5
 #include "mmu-mips.h"
 
 #define CFG_UART_BASE    UART1_BASE      /* Base of the UART channel */