diff options
author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-06 18:23:38 -0400 |
---|---|---|
committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 03:43:43 +0000 |
commit | f554c7873428018b482e57c6ba9c96e0e67d320c (patch) | |
tree | 766d3f654a32e2e2ac9065d34864786e44051f08 /firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |
parent | 7ab063a157cfbd4170621e890e1ad4688d94808a (diff) | |
download | rockbox-f554c7873428018b482e57c6ba9c96e0e67d320c.tar.gz rockbox-f554c7873428018b482e57c6ba9c96e0e67d320c.zip |
jz4760: Don't enable PLL1 until we need audio.
Change-Id: I6320ee9ac809da93c80e571d45f01e22c5bd1c40
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4760.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 47 |
1 files changed, 30 insertions, 17 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index 8472a7378f..7bbf6d36ae 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
@@ -18,7 +18,7 @@ | |||
18 | * KIND, either express or implied. | 18 | * KIND, either express or implied. |
19 | * | 19 | * |
20 | ****************************************************************************/ | 20 | ****************************************************************************/ |
21 | 21 | ||
22 | #include "config.h" | 22 | #include "config.h" |
23 | #include "cpu.h" | 23 | #include "cpu.h" |
24 | #include "mips.h" | 24 | #include "mips.h" |
@@ -289,7 +289,7 @@ void intr_handler(void) | |||
289 | register int irq = get_irq_number(); | 289 | register int irq = get_irq_number(); |
290 | if(UNLIKELY(irq < 0)) | 290 | if(UNLIKELY(irq < 0)) |
291 | return; | 291 | return; |
292 | 292 | ||
293 | ack_irq(irq); | 293 | ack_irq(irq); |
294 | if(LIKELY(irq >= 0)) | 294 | if(LIKELY(irq >= 0)) |
295 | irqvector[irq](); | 295 | irqvector[irq](); |
@@ -379,7 +379,7 @@ static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal | |||
379 | continue; | 379 | continue; |
380 | for (k = pll_n_min; k <= pll_n_max; k++) { | 380 | for (k = pll_n_min; k <= pll_n_max; k++) { |
381 | n = k; | 381 | n = k; |
382 | 382 | ||
383 | /* Limit: 1MHZ <= XIN/N <= 50MHZ */ | 383 | /* Limit: 1MHZ <= XIN/N <= 50MHZ */ |
384 | if ((xtal / n) < (1 * MHZ)) | 384 | if ((xtal / n) < (1 * MHZ)) |
385 | break; | 385 | break; |
@@ -396,8 +396,8 @@ static inline unsigned int pll_calc_m_n_od(unsigned int speed, unsigned int xtal | |||
396 | 396 | ||
397 | if (tmp < distance) { | 397 | if (tmp < distance) { |
398 | distance = tmp; | 398 | distance = tmp; |
399 | 399 | ||
400 | plcr_m_n_od = (j << CPPCR0_PLLM_LSB) | 400 | plcr_m_n_od = (j << CPPCR0_PLLM_LSB) |
401 | | (k << CPPCR0_PLLN_LSB) | 401 | | (k << CPPCR0_PLLN_LSB) |
402 | | (i << CPPCR0_PLLOD_LSB); | 402 | | (i << CPPCR0_PLLOD_LSB); |
403 | 403 | ||
@@ -430,12 +430,21 @@ static void pll0_init(unsigned int freq) | |||
430 | int div[6] = {1, 4, 4, 4, 4, 4}; | 430 | int div[6] = {1, 4, 4, 4, 4, 4}; |
431 | int usbdiv; | 431 | int usbdiv; |
432 | 432 | ||
433 | /* @ CPU_FREQ of 492MHZ, this means: | ||
434 | 492MHz CCLK | ||
435 | 123MHz HCLK | ||
436 | 123MHz H2CLK | ||
437 | 123MHz PCLK | ||
438 | 123MHz MCLK | ||
439 | 123MHZ SCLK ( must equal H2CLK or HCLK/2) | ||
440 | */ | ||
441 | |||
433 | /* set ahb **/ | 442 | /* set ahb **/ |
434 | REG32(HARB0_BASE) = 0x00300000; | 443 | REG32(HARB0_BASE) = 0x00300000; |
435 | REG32(0xb3070048) = 0x00000000; | 444 | REG32(0xb3070048) = 0x00000000; |
436 | REG32(HARB2_BASE) = 0x00FFFFFF; | 445 | REG32(HARB2_BASE) = 0x00FFFFFF; |
437 | 446 | ||
438 | cfcr = CPCCR_PCS | | 447 | cfcr = CPCCR_PCS | // no divisor on PLL for peripherals |
439 | (n2FR[div[0]] << CPCCR_CDIV_LSB) | | 448 | (n2FR[div[0]] << CPCCR_CDIV_LSB) | |
440 | (n2FR[div[1]] << CPCCR_HDIV_LSB) | | 449 | (n2FR[div[1]] << CPCCR_HDIV_LSB) | |
441 | (n2FR[div[2]] << CPCCR_H2DIV_LSB) | | 450 | (n2FR[div[2]] << CPCCR_H2DIV_LSB) | |
@@ -458,13 +467,13 @@ static void pll0_init(unsigned int freq) | |||
458 | else | 467 | else |
459 | cfcr &= ~CPCCR_ECS; | 468 | cfcr &= ~CPCCR_ECS; |
460 | 469 | ||
461 | cfcr &= ~CPCCR_MEM; /* mddr */ | 470 | cfcr &= ~CPCCR_MEM; /* Use mobile DDR / SDRAM */ |
462 | cfcr |= CPCCR_CE; | 471 | cfcr |= CPCCR_CE; |
463 | 472 | ||
464 | plcr1 = pll_calc_m_n_od(freq, CFG_EXTAL); | 473 | plcr1 = pll_calc_m_n_od(freq, CFG_EXTAL); |
465 | plcr1 |= (0x20 << CPPCR0_PLLST_LSB) /* PLL stable time */ | 474 | plcr1 |= (0x20 << CPPCR0_PLLST_LSB) /* PLL stable time */ |
466 | | CPPCR0_PLLEN; /* enable PLL */ | 475 | | CPPCR0_PLLEN; /* enable PLL */ |
467 | 476 | ||
468 | /* | 477 | /* |
469 | * Init USB Host clock, pllout2 must be n*48MHz | 478 | * Init USB Host clock, pllout2 must be n*48MHz |
470 | * For JZ4760b UHC - River. | 479 | * For JZ4760b UHC - River. |
@@ -488,7 +497,6 @@ void pll1_init(unsigned int freq) | |||
488 | { | 497 | { |
489 | register unsigned int plcr2; | 498 | register unsigned int plcr2; |
490 | 499 | ||
491 | /* set CPM_CPCCR_MEM only for ddr1 or ddr2 */ | ||
492 | plcr2 = pll_calc_m_n_od(freq, CFG_EXTAL) | 500 | plcr2 = pll_calc_m_n_od(freq, CFG_EXTAL) |
493 | | CPPCR1_PLL1EN; /* enable PLL1 */ | 501 | | CPPCR1_PLL1EN; /* enable PLL1 */ |
494 | 502 | ||
@@ -503,6 +511,11 @@ void pll1_init(unsigned int freq) | |||
503 | REG_CPM_CPPCR1 &= ~CPPCR1_LOCK; | 511 | REG_CPM_CPPCR1 &= ~CPPCR1_LOCK; |
504 | } | 512 | } |
505 | 513 | ||
514 | void pll1_disable(void) | ||
515 | { | ||
516 | REG_CPM_CPPCR1 &= ~CPPCR1_PLL1EN; | ||
517 | } | ||
518 | |||
506 | static void serial_setbrg(void) | 519 | static void serial_setbrg(void) |
507 | { | 520 | { |
508 | volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); | 521 | volatile u8 *uart_lcr = (volatile u8 *)(CFG_UART_BASE + OFF_LCR); |
@@ -548,10 +561,10 @@ int serial_preinit(void) | |||
548 | 561 | ||
549 | /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ | 562 | /* Set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */ |
550 | *uart_lcr = UARTLCR_WLEN_8 | UARTLCR_STOP1; | 563 | *uart_lcr = UARTLCR_WLEN_8 | UARTLCR_STOP1; |
551 | 564 | ||
552 | /* Set baud rate */ | 565 | /* Set baud rate */ |
553 | serial_setbrg(); | 566 | serial_setbrg(); |
554 | 567 | ||
555 | /* Enable UART unit, enable and clear FIFO */ | 568 | /* Enable UART unit, enable and clear FIFO */ |
556 | *uart_fcr = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS; | 569 | *uart_fcr = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS; |
557 | 570 | ||
@@ -626,10 +639,10 @@ void dma_preinit(void) | |||
626 | void ICODE_ATTR system_main(void) | 639 | void ICODE_ATTR system_main(void) |
627 | { | 640 | { |
628 | int i; | 641 | int i; |
629 | 642 | ||
630 | __dcache_writeback_all(); | 643 | __dcache_writeback_all(); |
631 | __icache_invalidate_all(); | 644 | __icache_invalidate_all(); |
632 | 645 | ||
633 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ | 646 | write_c0_status(1 << 28 | 1 << 10 ); /* Enable CP | Mask interrupt 2 */ |
634 | 647 | ||
635 | /* Disable all interrupts */ | 648 | /* Disable all interrupts */ |
@@ -638,8 +651,8 @@ void ICODE_ATTR system_main(void) | |||
638 | 651 | ||
639 | mmu_init(); | 652 | mmu_init(); |
640 | 653 | ||
641 | pll0_init(CPU_FREQ); | 654 | pll0_init(CPU_FREQ); // PLL0 drives everything but audio |
642 | pll1_init(CPU_FREQ); | 655 | pll1_disable(); // Leave PLL1 disabled until audio needs it |
643 | 656 | ||
644 | serial_preinit(); | 657 | serial_preinit(); |
645 | usb_preinit(); | 658 | usb_preinit(); |
@@ -673,7 +686,7 @@ void system_exception_wait(void) | |||
673 | void power_off(void) | 686 | void power_off(void) |
674 | { | 687 | { |
675 | REG_CPM_RSR = 0x0; | 688 | REG_CPM_RSR = 0x0; |
676 | 689 | ||
677 | /* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */ | 690 | /* Set minimum wakeup_n pin low-level assertion time for wakeup: 100ms */ |
678 | rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000)); | 691 | rtc_write_reg(RTC_HWFCR, HWFCR_WAIT_TIME(1000)); |
679 | 692 | ||