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| author | Solomon Peachy <pizza@shaftnet.org> | 2020-09-02 13:31:55 -0400 |
|---|---|---|
| committer | Solomon Peachy <pizza@shaftnet.org> | 2020-09-02 13:39:05 -0400 |
| commit | 546212a977270c3a8e8b8c0e2b5fd30ed612ddc5 (patch) | |
| tree | ee7b517f756a38bfe525f4535a0345bd8d2e749f /firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |
| parent | f913829d06f706e0f7df3b791835edd41fc487c4 (diff) | |
| download | rockbox-546212a977270c3a8e8b8c0e2b5fd30ed612ddc5.tar.gz rockbox-546212a977270c3a8e8b8c0e2b5fd30ed612ddc5.zip | |
jz4760: Dial down PIXCLK as low as possible
We don't use it on the X3. Should we ever get another jz4760 target
we can revisit this.
Change-Id: I591d02c7e47b35424b3c96b776b31a38e3c8ceee
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/system-jz4760.c')
| -rw-r--r-- | firmware/target/mips/ingenic_jz47xx/system-jz4760.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c index a8e40e4e31..ff87e5ad9e 100644 --- a/firmware/target/mips/ingenic_jz47xx/system-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/system-jz4760.c | |||
| @@ -503,6 +503,9 @@ static void pll0_init(unsigned int freq) | |||
| 503 | /* Init MSC clock; shoot for 48MHz base clock. */ | 503 | /* Init MSC clock; shoot for 48MHz base clock. */ |
| 504 | REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1); | 504 | REG_CPM_MSCCDR = MSCCDR_MCS | ((freq / 48000000) - 1); |
| 505 | 505 | ||
| 506 | /* Clock LCD clock as low as possible here */ | ||
| 507 | __cpm_set_pixdiv(2048 -1); | ||
| 508 | |||
| 506 | /* init PLL */ | 509 | /* init PLL */ |
| 507 | REG_CPM_CPCCR = cfcr; | 510 | REG_CPM_CPCCR = cfcr; |
| 508 | REG_CPM_CPPCR0 = plcr1; | 511 | REG_CPM_CPPCR0 = plcr1; |