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author | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-12-04 19:44:03 +0000 |
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committer | Maurus Cuelenaere <mcuelenaere@gmail.com> | 2008-12-04 19:44:03 +0000 |
commit | 7ea9e31658da4fce9c4a3e30838b82fda8eda287 (patch) | |
tree | d0470a3d41b30dd7d26487be9e29436c0162055a /firmware/target/mips/ingenic_jz47xx/codec-jz4740.c | |
parent | c848d2dd990e69a0a10a3f501f64575efbe25695 (diff) | |
download | rockbox-7ea9e31658da4fce9c4a3e30838b82fda8eda287.tar.gz rockbox-7ea9e31658da4fce9c4a3e30838b82fda8eda287.zip |
Ingenic targets:
* Get audio working (only noise atm)
* Clean up some stuff in USB
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19329 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/codec-jz4740.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/codec-jz4740.c | 59 |
1 files changed, 30 insertions, 29 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c index dec343a0da..d144a03553 100644 --- a/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c +++ b/firmware/target/mips/ingenic_jz47xx/codec-jz4740.c | |||
@@ -32,50 +32,52 @@ static int IS_WRITE_PCM; | |||
32 | 32 | ||
33 | static void i2s_codec_set_samplerate(unsigned short rate); | 33 | static void i2s_codec_set_samplerate(unsigned short rate); |
34 | 34 | ||
35 | static void i2s_codec_clear(void) | 35 | static void i2s_codec_reset(void) |
36 | { | 36 | { |
37 | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | | 37 | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | |
38 | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | | 38 | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | |
39 | ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); | 39 | ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); |
40 | udelay(10); | ||
41 | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | | ||
42 | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP ); | ||
40 | } | 43 | } |
41 | 44 | ||
42 | static void i2s_codec_init(void) | 45 | static void i2s_codec_init(void) |
43 | { | 46 | { |
44 | __aic_enable(); | 47 | __aic_enable(); |
45 | 48 | ||
46 | __aic_select_i2s(); | ||
47 | __i2s_internal_codec(); | 49 | __i2s_internal_codec(); |
50 | __i2s_as_slave(); | ||
51 | __i2s_select_i2s(); | ||
52 | __aic_select_i2s(); | ||
48 | 53 | ||
49 | __i2s_set_oss_sample_size(16); | 54 | __aic_disable_byteswap(); |
55 | __aic_disable_unsignadj(); | ||
56 | __aic_disable_mono2stereo(); | ||
50 | 57 | ||
51 | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | | 58 | i2s_codec_reset(); |
52 | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | | ||
53 | ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); /* reset */ | ||
54 | udelay(10); | ||
55 | REG_ICDC_CDCCR1 = (ICDC_CDCCR1_SW2ON | ICDC_CDCCR1_PDVR | ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_VRCGL | | ||
56 | ICDC_CDCCR1_VRCGH | ICDC_CDCCR1_HPOV0 | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP | | ||
57 | ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); | ||
58 | //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) | | ||
59 | REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) | | ||
60 | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6)); | ||
61 | 59 | ||
62 | REG_ICDC_CDCCR1 &= 0xfffffffc; | 60 | //REG_ICDC_CDCCR2 = (ICDC_CDCCR2_AINVOL(ICDC_CDCCR2_AINVOL_DB(0)) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) |
63 | 61 | REG_ICDC_CDCCR2 = ( ICDC_CDCCR2_AINVOL(23) | ICDC_CDCCR2_SMPR(ICDC_CDCCR2_SMPR_48) | |
64 | mdelay(15); | 62 | | ICDC_CDCCR2_HPVOL(ICDC_CDCCR2_HPVOL_6)); |
65 | REG_ICDC_CDCCR1 &= 0xffecffff; | ||
66 | REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG); | ||
67 | |||
68 | mdelay(600); | ||
69 | REG_ICDC_CDCCR1 &= 0xfff7ecff; | ||
70 | |||
71 | mdelay(2); | ||
72 | 63 | ||
73 | /* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */ | 64 | REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_SUSPD | ICDC_CDCCR1_RST); |
74 | REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~((1 << 29) | (1 << 28) | (1 << 26) | (1 << 27) | (1 << 14))) | ((1 << 24) | (1 << 25)); | 65 | |
66 | mdelay(15); | ||
67 | REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVR | ICDC_CDCCR1_VRCGL | ICDC_CDCCR1_VRCGH); | ||
68 | REG_ICDC_CDCCR1 |= (ICDC_CDCCR1_EDAC | ICDC_CDCCR1_HPCG); | ||
75 | 69 | ||
76 | REG_ICDC_CDCCR2 = ((REG_ICDC_CDCCR2 & ~(0x3)) | 3); | 70 | mdelay(600); |
71 | REG_ICDC_CDCCR1 &= ~(ICDC_CDCCR1_PDVRA | ICDC_CDCCR1_HPCG | ICDC_CDCCR1_PDHPM | ICDC_CDCCR1_PDHP); | ||
77 | 72 | ||
78 | i2s_codec_set_samplerate(44100); | 73 | mdelay(2); |
74 | |||
75 | /* CDCCR1.ELININ=0, CDCCR1.EMIC=0, CDCCR1.EADC=0, CDCCR1.SW1ON=0, CDCCR1.EDAC=1, CDCCR1.SW2ON=1, CDCCR1.HPMUTE=0 */ | ||
76 | REG_ICDC_CDCCR1 = (REG_ICDC_CDCCR1 & ~(ICDC_CDCCR1_ELININ | ICDC_CDCCR1_EMIC | ICDC_CDCCR1_EADC | | ||
77 | ICDC_CDCCR1_SW1ON | ICDC_CDCCR1_HPMUTE)) | (ICDC_CDCCR1_EDAC | ||
78 | | ICDC_CDCCR1_SW2ON); | ||
79 | |||
80 | REG_ICDC_CDCCR2 |= 3; | ||
79 | 81 | ||
80 | HP_on_off_flag = 0; /* HP is off */ | 82 | HP_on_off_flag = 0; /* HP is off */ |
81 | } | 83 | } |
@@ -296,7 +298,6 @@ void audiohw_mute(bool mute) | |||
296 | 298 | ||
297 | void audiohw_preinit(void) | 299 | void audiohw_preinit(void) |
298 | { | 300 | { |
299 | i2s_codec_init(); | ||
300 | } | 301 | } |
301 | 302 | ||
302 | void audiohw_postinit(void) | 303 | void audiohw_postinit(void) |
@@ -306,5 +307,5 @@ void audiohw_postinit(void) | |||
306 | 307 | ||
307 | void audiohw_init(void) | 308 | void audiohw_init(void) |
308 | { | 309 | { |
309 | 310 | i2s_codec_init(); | |
310 | } | 311 | } |