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author | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 00:44:55 -0400 |
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committer | Solomon Peachy <pizza@shaftnet.org> | 2020-08-07 11:42:45 -0400 |
commit | eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543 (patch) | |
tree | 8989f4d1bfe2c24d67d72026f97ec8e0cc11f949 /firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |
parent | 62146ed73513ec62b57163d229c6719b9349c640 (diff) | |
download | rockbox-eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543.tar.gz rockbox-eb0e41c1ccb0dcf35efa7e1434bb0e35c9df1543.zip |
jz4760: Support dynamic reclocking!
default/low speed is 192 MHz, Max is 576
Downclock PCLK/MCLK/etc to 96MHz to save a bit of juice
Honestly the high speed could be dialed down to, eg 384
as this thing is so bloody fast..
Change-Id: Ie65597c74290f1603e65f69dae8e75b59c8ba0b4
Diffstat (limited to 'firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c')
-rw-r--r-- | firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c index 0135c1ced9..6862262045 100644 --- a/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c +++ b/firmware/target/mips/ingenic_jz47xx/ata-sd-jz4760.c | |||
@@ -633,14 +633,23 @@ static inline unsigned int jz_sd_calc_clkrt(const int drive, unsigned int rate) | |||
633 | return clkrt; | 633 | return clkrt; |
634 | } | 634 | } |
635 | 635 | ||
636 | static inline void cpm_select_msc_clk(unsigned int rate) | 636 | #ifndef HAVE_ADJUSTABLE_CPU_FREQ |
637 | #define cpu_frequency __cpm_get_pllout2() | ||
638 | #endif | ||
639 | |||
640 | void cpm_select_msc_clk(void) | ||
637 | { | 641 | { |
638 | unsigned int div = __cpm_get_pllout2() / rate; | 642 | unsigned int div = cpu_frequency / SD_CLOCK_FAST; |
643 | |||
639 | if (div == 0) | 644 | if (div == 0) |
640 | div = 1; | 645 | div = 1; |
641 | 646 | ||
647 | if (div == __cpm_get_mscdiv()) | ||
648 | return; | ||
649 | |||
642 | REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); | 650 | REG_CPM_MSCCDR = MSCCDR_MCS | (div - 1); |
643 | DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); | 651 | DEBUG("MSCCLK == %x\n", REG_CPM_MSCCDR); |
652 | __cpm_enable_pll_change(); | ||
644 | } | 653 | } |
645 | 654 | ||
646 | /* Set the MMC clock frequency */ | 655 | /* Set the MMC clock frequency */ |
@@ -651,9 +660,8 @@ static void jz_sd_set_clock(const int drive, unsigned int rate) | |||
651 | jz_sd_stop_clock(drive); | 660 | jz_sd_stop_clock(drive); |
652 | 661 | ||
653 | /* select clock source from CPM */ | 662 | /* select clock source from CPM */ |
654 | cpm_select_msc_clk(rate); | 663 | cpm_select_msc_clk(); |
655 | 664 | ||
656 | __cpm_enable_pll_change(); | ||
657 | clkrt = jz_sd_calc_clkrt(drive, rate); | 665 | clkrt = jz_sd_calc_clkrt(drive, rate); |
658 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; | 666 | REG_MSC_CLKRT(MSC_CHN(drive)) = clkrt; |
659 | 667 | ||