diff options
author | Lorenzo Miori <memorys60@gmail.com> | 2013-02-23 16:59:49 +0100 |
---|---|---|
committer | Thomas Martitz <kugel@rockbox.org> | 2013-03-06 00:21:22 +0100 |
commit | 60592165ca998875e4bc46c4396c5a123a7e9dbb (patch) | |
tree | 60b53e6b733fd49bef249761789e97a4bedbef03 /firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h | |
parent | 3e4be68f8b596cf3467f993dc9a210a3d901ca1c (diff) | |
download | rockbox-60592165ca998875e4bc46c4396c5a123a7e9dbb.tar.gz rockbox-60592165ca998875e4bc46c4396c5a123a7e9dbb.zip |
Samsung YP-R0 hosted target code refactoring
As per title this patch aims at splitting common target
code and specific target code in a better way to
support future ports within the same environment
(e.g. Samsung YP-R1 where the Linux and the SoC
are the same, with differences in hardware devices
handling)
Change-Id: I67b4918c46403b184d3d8f42ab5aae7d01037fd0
Reviewed-on: http://gerrit.rockbox.org/409
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
Diffstat (limited to 'firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h')
-rw-r--r-- | firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h | 185 |
1 files changed, 185 insertions, 0 deletions
diff --git a/firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h b/firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h new file mode 100644 index 0000000000..e77f35fbb7 --- /dev/null +++ b/firmware/target/hosted/samsungypr/ypr0/r0GPIOIoctl.h | |||
@@ -0,0 +1,185 @@ | |||
1 | /* This file originates from the linux kernel provided in Samsung's YP-R0 Open | ||
2 | * Source package (second release, which includes some driver modules sources). | ||
3 | */ | ||
4 | |||
5 | #ifndef __IOCTL_GPIO_H__ | ||
6 | #define __IOCTL_GPIO_H__ | ||
7 | |||
8 | #include <sys/ioctl.h> | ||
9 | //#include "iomux.h" | ||
10 | |||
11 | typedef struct { | ||
12 | int num; | ||
13 | int mode; | ||
14 | int val; | ||
15 | }__attribute__((packed)) R0GPIOInfo; | ||
16 | |||
17 | |||
18 | #define IOCTL_GPIO_MAGIC 'G' | ||
19 | |||
20 | #define E_IOCTL_GPIO_SET_MUX 0 | ||
21 | #define E_IOCTL_GPIO_UNSET_MUX 1 | ||
22 | #define E_IOCTL_GPIO_SET_TYPE 2 | ||
23 | #define E_IOCTL_GPIO_SET_OUTPUT 3 | ||
24 | #define E_IOCTL_GPIO_SET_INPUT 4 | ||
25 | #define E_IOCTL_GPIO_SET_HIGH 5 | ||
26 | #define E_IOCTL_GPIO_SET_LOW 6 | ||
27 | #define E_IOCTL_GPIO_GET_VAL 7 | ||
28 | #define E_IOCTL_GPIO_IS_HIGH 8 | ||
29 | #define E_IOCTL_GPIO_MAX_NR 9 | ||
30 | |||
31 | #define DEV_CTRL_GPIO_SET_MUX _IOW(IOCTL_GPIO_MAGIC, 0, R0GPIOInfo) | ||
32 | #define DEV_CTRL_GPIO_UNSET_MUX _IOW(IOCTL_GPIO_MAGIC, 1, R0GPIOInfo) | ||
33 | #define DEV_CTRL_GPIO_SET_TYPE _IOW(IOCTL_GPIO_MAGIC, 2, R0GPIOInfo) | ||
34 | #define DEV_CTRL_GPIO_SET_OUTPUT _IOW(IOCTL_GPIO_MAGIC, 3, R0GPIOInfo) | ||
35 | #define DEV_CTRL_GPIO_SET_INPUT _IOW(IOCTL_GPIO_MAGIC, 4, R0GPIOInfo) | ||
36 | #define DEV_CTRL_GPIO_SET_HIGH _IOW(IOCTL_GPIO_MAGIC, 5, R0GPIOInfo) | ||
37 | #define DEV_CTRL_GPIO_SET_LOW _IOW(IOCTL_GPIO_MAGIC, 6, R0GPIOInfo) | ||
38 | #define DEV_CTRL_GPIO_GET_VAL _IOW(IOCTL_GPIO_MAGIC, 7, R0GPIOInfo) | ||
39 | #define DEV_CTRL_GPIO_IS_HIGH _IOW(IOCTL_GPIO_MAGIC, 8, R0GPIOInfo) | ||
40 | |||
41 | |||
42 | typedef enum | ||
43 | { | ||
44 | GPIO1_0 = 0, /* GPIO group 1 start */ | ||
45 | GPIO1_1, | ||
46 | GPIO1_2, | ||
47 | GPIO1_3, | ||
48 | GPIO1_4, | ||
49 | GPIO1_5, | ||
50 | GPIO1_6, | ||
51 | GPIO1_7, | ||
52 | GPIO1_8, | ||
53 | GPIO1_9, | ||
54 | GPIO1_10, | ||
55 | GPIO1_11, | ||
56 | GPIO1_12, | ||
57 | GPIO1_13, | ||
58 | GPIO1_14, | ||
59 | GPIO1_15, | ||
60 | GPIO1_16, | ||
61 | GPIO1_17, | ||
62 | GPIO1_18, | ||
63 | GPIO1_19, | ||
64 | GPIO1_20, | ||
65 | GPIO1_21, | ||
66 | GPIO1_22, | ||
67 | GPIO1_23, | ||
68 | GPIO1_24, | ||
69 | GPIO1_25, | ||
70 | GPIO1_26, | ||
71 | GPIO1_27, | ||
72 | GPIO1_28, | ||
73 | GPIO1_29, | ||
74 | GPIO1_30, | ||
75 | GPIO1_31, | ||
76 | GPIO2_0, /* GPIO group 2 start */ | ||
77 | GPIO2_1, | ||
78 | GPIO2_2, | ||
79 | GPIO2_3, | ||
80 | GPIO2_4, | ||
81 | GPIO2_5, | ||
82 | GPIO2_6, | ||
83 | GPIO2_7, | ||
84 | GPIO2_8, | ||
85 | GPIO2_9, | ||
86 | GPIO2_10, | ||
87 | GPIO2_11, | ||
88 | GPIO2_12, | ||
89 | GPIO2_13, | ||
90 | GPIO2_14, | ||
91 | GPIO2_15, | ||
92 | GPIO2_16, | ||
93 | GPIO2_17, | ||
94 | GPIO2_18, | ||
95 | GPIO2_19, | ||
96 | GPIO2_20, | ||
97 | GPIO2_21, | ||
98 | GPIO2_22, | ||
99 | GPIO2_23, | ||
100 | GPIO2_24, | ||
101 | GPIO2_25, | ||
102 | GPIO2_26, | ||
103 | GPIO2_27, | ||
104 | GPIO2_28, | ||
105 | GPIO2_29, | ||
106 | GPIO2_30, | ||
107 | GPIO2_31, | ||
108 | GPIO3_0, /* GPIO group 3 start */ | ||
109 | GPIO3_1, | ||
110 | GPIO3_2, | ||
111 | GPIO3_3, | ||
112 | GPIO3_4, | ||
113 | GPIO3_5, | ||
114 | GPIO3_6, | ||
115 | GPIO3_7, | ||
116 | GPIO3_8, | ||
117 | GPIO3_9, | ||
118 | GPIO3_10, | ||
119 | GPIO3_11, | ||
120 | GPIO3_12, | ||
121 | GPIO3_13, | ||
122 | GPIO3_14, | ||
123 | GPIO3_15, | ||
124 | GPIO3_16, | ||
125 | GPIO3_17, | ||
126 | GPIO3_18, | ||
127 | GPIO3_19, | ||
128 | GPIO3_20, | ||
129 | GPIO3_21, | ||
130 | GPIO3_22, | ||
131 | GPIO3_23, | ||
132 | GPIO3_24, | ||
133 | GPIO3_25, | ||
134 | GPIO3_26, | ||
135 | GPIO3_27, | ||
136 | GPIO3_28, | ||
137 | GPIO3_29, | ||
138 | GPIO3_30, | ||
139 | GPIO3_31, | ||
140 | }R0_MX37_GPIO; | ||
141 | |||
142 | typedef enum | ||
143 | { | ||
144 | CONFIG_ALT0, | ||
145 | CONFIG_ALT1, | ||
146 | CONFIG_ALT2, | ||
147 | CONFIG_ALT3, | ||
148 | CONFIG_ALT4, | ||
149 | CONFIG_ALT5, | ||
150 | CONFIG_ALT6, | ||
151 | CONFIG_ALT7, | ||
152 | CONFIG_GPIO, | ||
153 | CONFIG_SION = 0x01 << 4, | ||
154 | CONFIG_DEFAULT | ||
155 | } R0_MX37_PIN_CONFIG; | ||
156 | |||
157 | #ifndef __MACH_MX37_IOMUX_H__ | ||
158 | typedef enum | ||
159 | { | ||
160 | PAD_CTL_SRE_SLOW = 0x0 << 0, | ||
161 | PAD_CTL_SRE_FAST = 0x1 << 0, | ||
162 | PAD_CTL_DRV_LOW = 0x0 << 1, | ||
163 | PAD_CTL_DRV_MEDIUM = 0x1 << 1, | ||
164 | PAD_CTL_DRV_HIGH = 0x2 << 1, | ||
165 | PAD_CTL_DRV_MAX = 0x3 << 1, | ||
166 | PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, | ||
167 | PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, | ||
168 | PAD_CTL_100K_PD = 0x0 << 4, | ||
169 | PAD_CTL_47K_PU = 0x1 << 4, | ||
170 | PAD_CTL_100K_PU = 0x2 << 4, | ||
171 | PAD_CTL_22K_PU = 0x3 << 4, | ||
172 | PAD_CTL_PUE_KEEPER = 0x0 << 6, | ||
173 | PAD_CTL_PUE_PULL = 0x1 << 6, | ||
174 | PAD_CTL_PKE_NONE = 0x0 << 7, | ||
175 | PAD_CTL_PKE_ENABLE = 0x1 << 7, | ||
176 | PAD_CTL_HYS_NONE = 0x0 << 8, | ||
177 | PAD_CTL_HYS_ENABLE = 0x1 << 8, | ||
178 | PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9, | ||
179 | PAD_CTL_DDR_INPUT_DDR = 0x1 << 9, | ||
180 | PAD_CTL_DRV_VOT_LOW = 0x0 << 13, | ||
181 | PAD_CTL_DRV_VOT_HIGH = 0x1 << 13, | ||
182 | } R0_MX37_PAD_CONFIG; | ||
183 | #endif | ||
184 | |||
185 | #endif /* __IOCTL_GPIO__H__ */ | ||