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author | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-30 10:01:04 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2006-03-30 10:01:04 +0000 |
commit | e62152ddf9a7b4f8f7a719f8a3bfc5f1bae83fe3 (patch) | |
tree | b899b3503ae307fb89c7b5c419045407a957edfe /firmware/target/coldfire | |
parent | 8bdd92b05e2c87b0bae478610436f292c9d3b952 (diff) | |
download | rockbox-e62152ddf9a7b4f8f7a719f8a3bfc5f1bae83fe3.tar.gz rockbox-e62152ddf9a7b4f8f7a719f8a3bfc5f1bae83fe3.zip |
Better sound quality on the iAudio X5 using the correct MCLK frequency
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@9354 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire')
-rw-r--r-- | firmware/target/coldfire/iaudio/x5/system-x5.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/target/coldfire/iaudio/x5/system-x5.c b/firmware/target/coldfire/iaudio/x5/system-x5.c index dee605733f..97d5ecc715 100644 --- a/firmware/target/coldfire/iaudio/x5/system-x5.c +++ b/firmware/target/coldfire/iaudio/x5/system-x5.c | |||
@@ -37,7 +37,7 @@ void set_cpu_frequency(long frequency) | |||
37 | /* Refresh timer for bypass frequency */ | 37 | /* Refresh timer for bypass frequency */ |
38 | PLLCR &= ~1; /* Bypass mode */ | 38 | PLLCR &= ~1; /* Bypass mode */ |
39 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 39 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
40 | PLLCR = 0x13042045; | 40 | PLLCR = 0x13442045; |
41 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 41 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
42 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 42 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ |
43 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 43 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -54,7 +54,7 @@ void set_cpu_frequency(long frequency) | |||
54 | /* Refresh timer for bypass frequency */ | 54 | /* Refresh timer for bypass frequency */ |
55 | PLLCR &= ~1; /* Bypass mode */ | 55 | PLLCR &= ~1; /* Bypass mode */ |
56 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 56 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
57 | PLLCR = 0x16030045; | 57 | PLLCR = 0x16430045; |
58 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 58 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
59 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 59 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
60 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 60 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
@@ -70,7 +70,7 @@ void set_cpu_frequency(long frequency) | |||
70 | /* Refresh timer for bypass frequency */ | 70 | /* Refresh timer for bypass frequency */ |
71 | PLLCR &= ~1; /* Bypass mode */ | 71 | PLLCR &= ~1; /* Bypass mode */ |
72 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | 72 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); |
73 | PLLCR = 0x10800200; /* Power down PLL, but keep CLSEL and CRSEL */ | 73 | PLLCR = 0x10400200; /* Power down PLL, but keep CLSEL and CRSEL */ |
74 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 74 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
75 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 75 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
76 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 76 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |