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author | Marcin Bukat <marcin.bukat@gmail.com> | 2010-05-10 12:36:27 +0000 |
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committer | Marcin Bukat <marcin.bukat@gmail.com> | 2010-05-10 12:36:27 +0000 |
commit | 45c2a6d3146aa4a40bf7f4bcc529d4e2f0d1cb17 (patch) | |
tree | 4e764c945da4d3b6d7b2101b0e4001a95439fe23 /firmware/target/coldfire/mpio/hd200/system-hd200.c | |
parent | 90de864d890c63615b269fee4493867046e8c9dc (diff) | |
download | rockbox-45c2a6d3146aa4a40bf7f4bcc529d4e2f0d1cb17.tar.gz rockbox-45c2a6d3146aa4a40bf7f4bcc529d4e2f0d1cb17.zip |
HD200 - Reduce wait states when writing to lcd.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25927 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/mpio/hd200/system-hd200.c')
-rw-r--r-- | firmware/target/coldfire/mpio/hd200/system-hd200.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/firmware/target/coldfire/mpio/hd200/system-hd200.c b/firmware/target/coldfire/mpio/hd200/system-hd200.c index 06628c0835..f7e270e094 100644 --- a/firmware/target/coldfire/mpio/hd200/system-hd200.c +++ b/firmware/target/coldfire/mpio/hd200/system-hd200.c | |||
@@ -90,7 +90,7 @@ void cf_set_cpu_frequency(long frequency) | |||
90 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 90 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
91 | PLLCR = 0x05028045 | (PLLCR & 0x70C00000); | 91 | PLLCR = 0x05028045 | (PLLCR & 0x70C00000); |
92 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 92 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
93 | CSCR3 = 0x00000980; /* LCD: 0 wait states */ | 93 | CSCR3 = 0x00000180; /* LCD: 0 wait states */ |
94 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | 94 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. |
95 | This may take up to 10ms! */ | 95 | This may take up to 10ms! */ |
96 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | 96 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); |
@@ -111,7 +111,7 @@ void cf_set_cpu_frequency(long frequency) | |||
111 | /* Power down PLL, but keep CLSEL and CRSEL */ | 111 | /* Power down PLL, but keep CLSEL and CRSEL */ |
112 | PLLCR = 0x00000200 | (PLLCR & 0x70C00000); | 112 | PLLCR = 0x00000200 | (PLLCR & 0x70C00000); |
113 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | 113 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ |
114 | CSCR3 = 0x00000980; /* LCD: 0 wait states */ | 114 | CSCR3 = 0x00000180; /* LCD: 0 wait states */ |
115 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | 115 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ |
116 | cpu_frequency = CPUFREQ_DEFAULT; | 116 | cpu_frequency = CPUFREQ_DEFAULT; |
117 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); | 117 | IDECONFIG1 = (1<<28)|(1<<20)|(1<<18)|(1<<13)|(1<<10); |