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author | Jens Arnold <amiconn@rockbox.org> | 2006-11-02 20:50:50 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2006-11-02 20:50:50 +0000 |
commit | 83aded979f074b6d48cd05db8f7f991e51372e38 (patch) | |
tree | b8bad1edd08bee7d8659cb1bb582fc305a9d70fa /firmware/target/coldfire/iriver | |
parent | d86350c9fad03356990e0844f1d35502e35b1d3b (diff) | |
download | rockbox-83aded979f074b6d48cd05db8f7f991e51372e38.tar.gz rockbox-83aded979f074b6d48cd05db8f7f991e51372e38.zip |
H300: (1) Use DMA for LCD updates, with auto-aligned line reads. Speeds up LCD updates by ~ 75% at 11MHz and 45MHz. Only ~ 11% speedup at 124MHz due to (2). (2) Less aggressive LCD transfer timing at 124MHz. With the previous timing, slightly corrupted display contents was reported, and with DMA transfers at least 4 waitstates are needed to make updates work at all. * A table in system-iriver.c shows settings for all integer multiples of the base clock frequency (info for developers, not yet complete).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@11418 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver')
-rwxr-xr-x | firmware/target/coldfire/iriver/h300/lcd-as-h300.S | 96 | ||||
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 24 |
2 files changed, 23 insertions, 97 deletions
diff --git a/firmware/target/coldfire/iriver/h300/lcd-as-h300.S b/firmware/target/coldfire/iriver/h300/lcd-as-h300.S index c6c1c76136..ae55dfb224 100755 --- a/firmware/target/coldfire/iriver/h300/lcd-as-h300.S +++ b/firmware/target/coldfire/iriver/h300/lcd-as-h300.S | |||
@@ -22,102 +22,6 @@ | |||
22 | 22 | ||
23 | .section .icode, "ax", @progbits | 23 | .section .icode, "ax", @progbits |
24 | 24 | ||
25 | .align 2 | ||
26 | .global lcd_write_data | ||
27 | .type lcd_write_data, @function | ||
28 | |||
29 | lcd_write_data: | ||
30 | move.l (4, %sp), %a0 /* data pointer */ | ||
31 | move.l (8, %sp), %d0 /* length in words */ | ||
32 | add.l %d0, %d0 /* words -> bytes */ | ||
33 | add.l %a0, %d0 /* -> end address */ | ||
34 | lea.l 0xf0000002, %a1 /* LCD data port */ | ||
35 | |||
36 | move.l %a0, %d1 | ||
37 | btst.l #1, %d1 /* already longword aligned? */ | ||
38 | beq.s .word1_end /* yes: skip initial word copy */ | ||
39 | |||
40 | move.w (%a0)+, (%a1) /* transfer initial word */ | ||
41 | |||
42 | .word1_end: /* now longword aligned */ | ||
43 | moveq.l #28, %d1 | ||
44 | add.l %a0, %d1 | ||
45 | and.l #0xFFFFFFF0,%d1 /* %d1 = first line bound + 16 */ | ||
46 | cmp.l %d1, %d0 /* at least one full line to send? */ | ||
47 | blo.s .long2_start /* no: skip to trailing longword handling */ | ||
48 | |||
49 | lea.l (-16, %sp), %sp /* free up some registers */ | ||
50 | movem.l %d2-%d4/%a2, (%sp) | ||
51 | |||
52 | subq.l #8, %d1 | ||
53 | subq.l #8, %d1 /* %d1 = first line bound */ | ||
54 | |||
55 | cmp.l %a0, %d1 /* any leading longwords? */ | ||
56 | bls.s .long1_end /* no: skip leading long loop */ | ||
57 | |||
58 | .long1_loop: | ||
59 | move.l (%a0)+, %d2 /* read longword */ | ||
60 | swap %d2 /* send data to LCD in correct order...*/ | ||
61 | move.w %d2, (%a1) | ||
62 | swap %d2 | ||
63 | move.w %d2, (%a1) | ||
64 | cmp.l %a0, %d1 /* run %a0 up to first line bound */ | ||
65 | bhi.s .long1_loop | ||
66 | |||
67 | .long1_end: | ||
68 | move.l %d0, %a2 | ||
69 | lea.l (-14, %a2), %a2 /* %a2 = end address - 14 (one line/pass) */ | ||
70 | |||
71 | /* burst-optimised line transfers */ | ||
72 | .line_loop: | ||
73 | movem.l (%a0), %d1-%d4 /* burst-read line */ | ||
74 | lea.l (16, %a0), %a0 /* increment address */ | ||
75 | swap %d1 /* send data to LCD in correct order... */ | ||
76 | move.w %d1, (%a1) | ||
77 | swap %d1 | ||
78 | move.w %d1, (%a1) | ||
79 | swap %d2 | ||
80 | move.w %d2, (%a1) | ||
81 | swap %d2 | ||
82 | move.w %d2, (%a1) | ||
83 | swap %d3 | ||
84 | move.w %d3, (%a1) | ||
85 | swap %d3 | ||
86 | move.w %d3, (%a1) | ||
87 | swap %d4 | ||
88 | move.w %d4, (%a1) | ||
89 | swap %d4 | ||
90 | move.w %d4, (%a1) | ||
91 | cmp.l %a0, %a2 /* run %a0 up to last line bound */ | ||
92 | bhi.s .line_loop | ||
93 | |||
94 | movem.l (%sp), %d2-%d4/%a2 | ||
95 | lea.l (16, %sp), %sp /* restore registers */ | ||
96 | |||
97 | .long2_start: | ||
98 | subq.l #2, %d0 /* account for handling 2 words per loop */ | ||
99 | cmp.l %a0, %d0 /* any (trailing longwords? */ | ||
100 | bls.s .long2_end /* no: skip trailing longword loop */ | ||
101 | |||
102 | .long2_loop: | ||
103 | move.l (%a0)+, %d1 /* read longword */ | ||
104 | swap %d1 /* send data to LCD in correct order */ | ||
105 | move.w %d1, (%a1) | ||
106 | swap %d1 | ||
107 | move.w %d1, (%a1) | ||
108 | cmp.l %a0, %d0 /* run %a0 up to last long bound */ | ||
109 | bhi.s .long2_loop | ||
110 | |||
111 | .long2_end: | ||
112 | blo.s .word2_end /* no final word: skip */ | ||
113 | move.w (%a0)+, (%a1) /* transfer final word */ | ||
114 | |||
115 | .word2_end: | ||
116 | rts | ||
117 | .lcd_write_data_end: | ||
118 | .size lcd_write_data, .lcd_write_data_end - lcd_write_data | ||
119 | |||
120 | |||
121 | /* lcd_write_yuv420_lines(), based on lcd-as-x5.S | 25 | /* lcd_write_yuv420_lines(), based on lcd-as-x5.S |
122 | * | 26 | * |
123 | * See http://en.wikipedia.org/wiki/YCbCr | 27 | * See http://en.wikipedia.org/wiki/YCbCr |
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index 5f404fb8cf..3517788641 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -24,6 +24,28 @@ | |||
24 | #include "timer.h" | 24 | #include "timer.h" |
25 | #include "pcf50606.h" | 25 | #include "pcf50606.h" |
26 | 26 | ||
27 | /* Settings for all possible clock frequencies (with properly working timers) | ||
28 | * | ||
29 | * xxx_REFRESH_TIMER below | ||
30 | * system.h, CPUFREQ_xxx_MULT | | ||
31 | * | | | ||
32 | * V V | ||
33 | * Refreshtim. IDECONFIG1/IDECONFIG2 | ||
34 | * CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait | ||
35 | * --------------------------------------------------------------------------------------- | ||
36 | * 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0 | ||
37 | * 22579200 2 0x15c4e005 10 4 0x0180 0x0180 0x0180 1 0 0 | ||
38 | * 33868800 3 0x13c46005 15 7 0x0180 0x0180 0x0180 1 0 0 | ||
39 | * 45158400 4 0x15c4e001 21 10 0x0580 0x0180 0x0580 1 0 0 | ||
40 | * 56448000 5 0x12c4e005 26 12 0x0580 0x0980 | ||
41 | * 67737600 6 0x13c46001 32 15 0x0980 0x0d80 | ||
42 | * 79027200 7 0x13c52001 37 18 0x0980 0x1180 | ||
43 | * 90316800 8 0x13c5e001 43 21 0x0d80 0x1580 | ||
44 | * 101606400 9 0x11c48005 48 23 0x0d80 0x1980 | ||
45 | * 112896000 10 0x11c4e005 54 26 0x1180 0x1d80 | ||
46 | * 124185600 11 0x11c56005 59 29 0x1180 0x1180 0x2180 2 1 2 | ||
47 | */ | ||
48 | |||
27 | #if MEM < 32 | 49 | #if MEM < 32 |
28 | #define MAX_REFRESH_TIMER 59 | 50 | #define MAX_REFRESH_TIMER 59 |
29 | #define NORMAL_REFRESH_TIMER 21 | 51 | #define NORMAL_REFRESH_TIMER 21 |
@@ -61,7 +83,7 @@ void set_cpu_frequency(long frequency) | |||
61 | RECALC_DELAYS(CPUFREQ_MAX); | 83 | RECALC_DELAYS(CPUFREQ_MAX); |
62 | PLLCR = 0x11c56005; | 84 | PLLCR = 0x11c56005; |
63 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
64 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | 86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ |
65 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 87 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
66 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ | 88 | CSCR3 = 0x00002180; /* USBOTG: 8 wait states */ |
67 | #endif | 89 | #endif |