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author | Linus Nielsen Feltzing <linus@haxx.se> | 2007-02-05 00:01:29 +0000 |
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committer | Linus Nielsen Feltzing <linus@haxx.se> | 2007-02-05 00:01:29 +0000 |
commit | 1eff300f18012badab1803fc8b947cee334813ee (patch) | |
tree | c4564955bc3147265a8eff0650e7138c50eb00f2 /firmware/target/coldfire/iriver | |
parent | eee9798d8dc7ef80e7330d1b5e14a6aa4404bf66 (diff) | |
download | rockbox-1eff300f18012badab1803fc8b947cee334813ee.tar.gz rockbox-1eff300f18012badab1803fc8b947cee334813ee.zip |
New PLL calculations to make sure that PLLDIV != 0. This seems to solve the problem with the troublesome H140 batch from OutletMP3.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12201 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iriver')
-rw-r--r-- | firmware/target/coldfire/iriver/system-iriver.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/firmware/target/coldfire/iriver/system-iriver.c b/firmware/target/coldfire/iriver/system-iriver.c index b67a4228b9..32fc44f963 100644 --- a/firmware/target/coldfire/iriver/system-iriver.c +++ b/firmware/target/coldfire/iriver/system-iriver.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include "pcf50606.h" | 25 | #include "pcf50606.h" |
26 | 26 | ||
27 | /* Settings for all possible clock frequencies (with properly working timers) | 27 | /* Settings for all possible clock frequencies (with properly working timers) |
28 | * NOTE: Some 5249 chips don't like having PLLDIV set to 0. We must avoid that! | ||
28 | * | 29 | * |
29 | * xxx_REFRESH_TIMER below | 30 | * xxx_REFRESH_TIMER below |
30 | * system.h, CPUFREQ_xxx_MULT | | 31 | * system.h, CPUFREQ_xxx_MULT | |
@@ -34,16 +35,16 @@ | |||
34 | * CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait | 35 | * CPUCLK/Hz MULT PLLCR 16MB 32MB CSCR0 CSCR1 CSCR3 CS2Pre CS2Post CS2Wait |
35 | * --------------------------------------------------------------------------------------- | 36 | * --------------------------------------------------------------------------------------- |
36 | * 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0 | 37 | * 11289600 1 0x10c00200 4 1 0x0180 0x0180 0x0180 1 0 0 |
37 | * 22579200 2 0x15c4e005 10 4 0x0180 0x0180 0x0180 1 0 0 | 38 | * 22579200 2 0x15c9e025 10 4 0x0180 0x0180 0x0180 1 0 0 |
38 | * 33868800 3 0x13c46005 15 7 0x0180 0x0180 0x0180 1 0 0 | 39 | * 33868800 3 0x13c8e025 15 7 0x0180 0x0180 0x0180 1 0 0 |
39 | * 45158400 4 0x15c4e001 21 10 0x0580 0x0180 0x0580 1 0 0 | 40 | * 45158400 4 0x15c9e021 21 10 0x0580 0x0180 0x0580 1 0 0 |
40 | * 56448000 5 0x12c4e005 26 12 0x0580 0x0980 | 41 | * 56448000 5 0x12c9e025 26 12 0x0580 0x0980 |
41 | * 67737600 6 0x13c46001 32 15 0x0980 0x0d80 | 42 | * 67737600 6 0x13c8e021 32 15 0x0980 0x0d80 |
42 | * 79027200 7 0x13c52001 37 18 0x0980 0x1180 | 43 | * 79027200 7 0x13ca6021 37 18 0x0980 0x1180 |
43 | * 90316800 8 0x13c5e001 43 21 0x0d80 0x1580 | 44 | * 90316800 8 0x13cbe021 43 21 0x0d80 0x1580 |
44 | * 101606400 9 0x11c48005 48 23 0x0d80 0x1980 | 45 | * 101606400 9 0x11c92025 48 23 0x0d80 0x1980 |
45 | * 112896000 10 0x11c4e005 54 26 0x1180 0x1d80 | 46 | * 112896000 10 0x11c9e025 54 26 0x1180 0x1d80 |
46 | * 124185600 11 0x11c56005 59 29 0x1180 0x1180 0x2180 2 1 2 | 47 | * 124185600 11 0x11cae025 59 29 0x1180 0x1180 0x2180 2 1 2 |
47 | */ | 48 | */ |
48 | 49 | ||
49 | #if MEM < 32 | 50 | #if MEM < 32 |
@@ -81,7 +82,7 @@ void set_cpu_frequency(long frequency) | |||
81 | PLLCR &= ~1; /* Bypass mode */ | 82 | PLLCR &= ~1; /* Bypass mode */ |
82 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 83 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
83 | RECALC_DELAYS(CPUFREQ_MAX); | 84 | RECALC_DELAYS(CPUFREQ_MAX); |
84 | PLLCR = 0x01856005 | (PLLCR & 0x70400000); | 85 | PLLCR = 0x018ae025 | (PLLCR & 0x70400000); |
85 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | 86 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ |
86 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ | 87 | CSCR1 = 0x00001580; /* LCD: 5 wait states */ |
87 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 88 | #if CONFIG_USBOTG == USBOTG_ISP1362 |
@@ -108,7 +109,7 @@ void set_cpu_frequency(long frequency) | |||
108 | PLLCR &= ~1; /* Bypass mode */ | 109 | PLLCR &= ~1; /* Bypass mode */ |
109 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | 110 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); |
110 | RECALC_DELAYS(CPUFREQ_NORMAL); | 111 | RECALC_DELAYS(CPUFREQ_NORMAL); |
111 | PLLCR = 0x0385e005 | (PLLCR & 0x70400000); | 112 | PLLCR = 0x038be025 | (PLLCR & 0x70400000); |
112 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | 113 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ |
113 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | 114 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ |
114 | #if CONFIG_USBOTG == USBOTG_ISP1362 | 115 | #if CONFIG_USBOTG == USBOTG_ISP1362 |