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author | Michael Sevakis <jethead71@rockbox.org> | 2006-09-12 14:20:29 +0000 |
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committer | Michael Sevakis <jethead71@rockbox.org> | 2006-09-12 14:20:29 +0000 |
commit | 3bee89ed44680c0abeffe4f1c6e69f9928b00e89 (patch) | |
tree | fc2760e29bc595a0a00f03174909adcde6bf4350 /firmware/target/coldfire/iaudio/x5/pcf50606-x5.c | |
parent | bc0943e922fde5c13ba4e01b9e372db6ee598765 (diff) | |
download | rockbox-3bee89ed44680c0abeffe4f1c6e69f9928b00e89.tar.gz rockbox-3bee89ed44680c0abeffe4f1c6e69f9928b00e89.zip |
Improved handling of the ONKEY1S interrupt. Off for the remote must be explicitly mapped now.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@10932 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iaudio/x5/pcf50606-x5.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/x5/pcf50606-x5.c | 40 |
1 files changed, 25 insertions, 15 deletions
diff --git a/firmware/target/coldfire/iaudio/x5/pcf50606-x5.c b/firmware/target/coldfire/iaudio/x5/pcf50606-x5.c index f0e11f088d..eaecc5bef6 100644 --- a/firmware/target/coldfire/iaudio/x5/pcf50606-x5.c +++ b/firmware/target/coldfire/iaudio/x5/pcf50606-x5.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include "debug.h" | 26 | #include "debug.h" |
27 | #include "string.h" | 27 | #include "string.h" |
28 | #include "generic_i2c.h" | 28 | #include "generic_i2c.h" |
29 | #include "powermgmt.h" | ||
29 | 30 | ||
30 | void pcf50606_sda_output(void) | 31 | void pcf50606_sda_output(void) |
31 | { | 32 | { |
@@ -154,7 +155,13 @@ static void set_voltages(void) | |||
154 | 155 | ||
155 | void pcf50606_init(void) | 156 | void pcf50606_init(void) |
156 | { | 157 | { |
157 | unsigned char read[3]; | 158 | /* inital data is interrupt masks */ |
159 | unsigned char data[3] = | ||
160 | { | ||
161 | ~0x04, /* unmask ONKEY1S */ | ||
162 | ~0x00, | ||
163 | ~0x00 | ||
164 | }; | ||
158 | 165 | ||
159 | /* Bit banged I2C */ | 166 | /* Bit banged I2C */ |
160 | or_l(0x00001000, &GPIO1_OUT); | 167 | or_l(0x00001000, &GPIO1_OUT); |
@@ -169,10 +176,10 @@ void pcf50606_init(void) | |||
169 | /* make sure GPI0 interrupt is off before unmasking anything */ | 176 | /* make sure GPI0 interrupt is off before unmasking anything */ |
170 | and_l(~0xF, &INTPRI5); /* INT32 - Priority 0 (Off) */ | 177 | and_l(~0xF, &INTPRI5); /* INT32 - Priority 0 (Off) */ |
171 | 178 | ||
172 | /* unmask ONKEY1S - ONKEY held low for 1 second */ | 179 | /* unmask the PMU interrupts we want to service */ |
173 | pcf50606_write(0x05, ~0x04); | 180 | pcf50606_write_multiple(0x05, data, 3); |
174 | /* clear INT1-3 as these are left set after standby */ | 181 | /* clear INT1-3 as these are left set after standby */ |
175 | pcf50606_read_multiple(0x02, read, 3); | 182 | pcf50606_read_multiple(0x02, data, 3); |
176 | 183 | ||
177 | /* Set to read pcf50606 INT but keep GPI0 off until init completes */ | 184 | /* Set to read pcf50606 INT but keep GPI0 off until init completes */ |
178 | and_l(~0x00000001, &GPIO_ENABLE); | 185 | and_l(~0x00000001, &GPIO_ENABLE); |
@@ -184,11 +191,6 @@ void pcf50606_init(void) | |||
184 | pcf50606_write(0x39, 0x00); /* GPOOD0 = green led OFF */ | 191 | pcf50606_write(0x39, 0x00); /* GPOOD0 = green led OFF */ |
185 | pcf50606_write(0x3a, 0x00); /* GPOOD1 = red led OFF */ | 192 | pcf50606_write(0x3a, 0x00); /* GPOOD1 = red led OFF */ |
186 | 193 | ||
187 | /* D305A datasheet says PWM clock frequency should be 400Hz - 2000Hz so | ||
188 | * I changed it from 7kHz to 512Hz. The lower frequency looks the same. | ||
189 | * GPO1 is also inverted so that display brightness increases with PWM | ||
190 | * cycle. | ||
191 | */ | ||
192 | pcf50606_write(0x35, 0x11); /* Backlight PWM = 512Hz, 8/16, Active */ | 194 | pcf50606_write(0x35, 0x11); /* Backlight PWM = 512Hz, 8/16, Active */ |
193 | #ifdef BOOTLOADER | 195 | #ifdef BOOTLOADER |
194 | /* Backlight starts OFF in bootloader */ | 196 | /* Backlight starts OFF in bootloader */ |
@@ -199,7 +201,14 @@ void pcf50606_init(void) | |||
199 | #endif | 201 | #endif |
200 | 202 | ||
201 | /* allow GPI0 interrupts from PMU now */ | 203 | /* allow GPI0 interrupts from PMU now */ |
202 | or_l(0x6, &INTPRI5); /* INT32 - Priority 6 */ | 204 | or_l(0x3, &INTPRI5); /* INT32 - Priority 3 */ |
205 | } | ||
206 | |||
207 | void pcf50606_reset_timeout(void) | ||
208 | { | ||
209 | int level = set_irq_level(HIGHEST_IRQ_LEVEL); | ||
210 | pcf50606_write(0x08, pcf50606_read(0x08) | 0x02); /* OOCC1 - TOTRST=1 */ | ||
211 | set_irq_level(level); | ||
203 | } | 212 | } |
204 | 213 | ||
205 | /* Handles interrupts generated by the pcf50606 */ | 214 | /* Handles interrupts generated by the pcf50606 */ |
@@ -208,15 +217,16 @@ void GPI0(void) | |||
208 | { | 217 | { |
209 | char read[3]; /* 0 = INT1, 1 = INT2, 2 = INT3 */ | 218 | char read[3]; /* 0 = INT1, 1 = INT2, 2 = INT3 */ |
210 | 219 | ||
211 | /* Clear pending interrupts from pcf50606 - reading all INT* registers | 220 | /* clear pending interrupts from pcf50606 */ |
212 | resets the INT pin to high */ | ||
213 | pcf50606_read_multiple(0x02, read, 3); | 221 | pcf50606_read_multiple(0x02, read, 3); |
214 | 222 | ||
215 | if (read[0] & 0x04) | 223 | if (read[0] & 0x04) |
216 | { | 224 | { |
217 | /** ONKEY1S **/ | 225 | /* ONKEY1S */ |
218 | /* reset timeout or else pcf50606 will go into standby in 8s */ | 226 | if (GPIO_READ & 0x02000000) |
219 | pcf50606_write(0x08, pcf50606_read(0x08) | 0x02); /* OOCC1 - TOTRST=1 */ | 227 | sys_poweroff(); /* main ONKEY */ |
228 | else | ||
229 | pcf50606_reset_timeout(); /* remote ONKEY */ | ||
220 | } | 230 | } |
221 | 231 | ||
222 | /* Clear pending GPI0 interrupts */ | 232 | /* Clear pending GPI0 interrupts */ |