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author | Jens Arnold <amiconn@rockbox.org> | 2007-03-05 00:04:00 +0000 |
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committer | Jens Arnold <amiconn@rockbox.org> | 2007-03-05 00:04:00 +0000 |
commit | 8876018d25c6a56cce118482c1372bbff344cb23 (patch) | |
tree | a66dca10bf92674c655b9862fd366ecc77bba76a /firmware/target/coldfire/iaudio/system-iaudio.c | |
parent | ee07215d506def8d3483f4adf6e1d4ae51c10c52 (diff) | |
download | rockbox-8876018d25c6a56cce118482c1372bbff344cb23.tar.gz rockbox-8876018d25c6a56cce118482c1372bbff344cb23.zip |
Bring up the M5 port to a working stage: Extended numerous explicit checks for IAUDIO_X5 to also check for IAUDIO_M5, moved code around the target tree, added preliminary background for the sim.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@12610 a1c6a512-1295-4272-9138-f99709370657
Diffstat (limited to 'firmware/target/coldfire/iaudio/system-iaudio.c')
-rw-r--r-- | firmware/target/coldfire/iaudio/system-iaudio.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/firmware/target/coldfire/iaudio/system-iaudio.c b/firmware/target/coldfire/iaudio/system-iaudio.c new file mode 100644 index 0000000000..30a4f6e71b --- /dev/null +++ b/firmware/target/coldfire/iaudio/system-iaudio.c | |||
@@ -0,0 +1,90 @@ | |||
1 | /*************************************************************************** | ||
2 | * __________ __ ___. | ||
3 | * Open \______ \ ____ ____ | | _\_ |__ _______ ___ | ||
4 | * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ / | ||
5 | * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < < | ||
6 | * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \ | ||
7 | * \/ \/ \/ \/ \/ | ||
8 | * $Id$ | ||
9 | * | ||
10 | * Copyright (C) 2006 by Linus Nielsen Feltzing | ||
11 | * | ||
12 | * All files in this archive are subject to the GNU General Public License. | ||
13 | * See the file COPYING in the source tree root for full license agreement. | ||
14 | * | ||
15 | * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY | ||
16 | * KIND, either express or implied. | ||
17 | * | ||
18 | ****************************************************************************/ | ||
19 | #include "config.h" | ||
20 | #include "cpu.h" | ||
21 | #include "kernel.h" | ||
22 | #include "system.h" | ||
23 | #include "power.h" | ||
24 | #include "timer.h" | ||
25 | #include "pcf50606.h" | ||
26 | |||
27 | #define MAX_REFRESH_TIMER 59 | ||
28 | #define NORMAL_REFRESH_TIMER 21 | ||
29 | #define DEFAULT_REFRESH_TIMER 4 | ||
30 | |||
31 | #define RECALC_DELAYS(f) \ | ||
32 | pcf50606_i2c_recalc_delay(f) | ||
33 | |||
34 | void set_cpu_frequency (long) __attribute__ ((section (".icode"))); | ||
35 | void set_cpu_frequency(long frequency) | ||
36 | { | ||
37 | switch(frequency) | ||
38 | { | ||
39 | case CPUFREQ_MAX: | ||
40 | DCR = (0x8200 | DEFAULT_REFRESH_TIMER); | ||
41 | /* Refresh timer for bypass frequency */ | ||
42 | PLLCR &= ~1; /* Bypass mode */ | ||
43 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
44 | RECALC_DELAYS(CPUFREQ_MAX); | ||
45 | PLLCR = 0x03042045 | (PLLCR & 0x70C00000); | ||
46 | CSCR0 = 0x00001180; /* Flash: 4 wait states */ | ||
47 | CSCR1 = 0x00000980; /* LCD: 2 wait states */ | ||
48 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | ||
49 | This may take up to 10ms! */ | ||
50 | timers_adjust_prescale(CPUFREQ_MAX_MULT, true); | ||
51 | DCR = (0x8200 | MAX_REFRESH_TIMER); /* Refresh timer */ | ||
52 | cpu_frequency = CPUFREQ_MAX; | ||
53 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
54 | IDECONFIG2 = 0x40000 | (1 << 8); /* TA enable + CS2wait */ | ||
55 | break; | ||
56 | |||
57 | case CPUFREQ_NORMAL: | ||
58 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
59 | /* Refresh timer for bypass frequency */ | ||
60 | PLLCR &= ~1; /* Bypass mode */ | ||
61 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, false); | ||
62 | RECALC_DELAYS(CPUFREQ_NORMAL); | ||
63 | PLLCR = 0x06030045 | (PLLCR & 0x70C00000); | ||
64 | CSCR0 = 0x00000580; /* Flash: 1 wait state */ | ||
65 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
66 | while(!(PLLCR & 0x80000000)) {}; /* Wait until the PLL has locked. | ||
67 | This may take up to 10ms! */ | ||
68 | timers_adjust_prescale(CPUFREQ_NORMAL_MULT, true); | ||
69 | DCR = (0x8000 | NORMAL_REFRESH_TIMER); /* Refresh timer */ | ||
70 | cpu_frequency = CPUFREQ_NORMAL; | ||
71 | IDECONFIG1 = 0x106000 | (5 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
72 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | ||
73 | break; | ||
74 | default: | ||
75 | DCR = (DCR & ~0x01ff) | DEFAULT_REFRESH_TIMER; | ||
76 | /* Refresh timer for bypass frequency */ | ||
77 | PLLCR &= ~1; /* Bypass mode */ | ||
78 | timers_adjust_prescale(CPUFREQ_DEFAULT_MULT, true); | ||
79 | RECALC_DELAYS(CPUFREQ_DEFAULT); | ||
80 | /* Power down PLL, but keep CLSEL and CRSEL */ | ||
81 | PLLCR = 0x00000200 | (PLLCR & 0x70C00000); | ||
82 | CSCR0 = 0x00000180; /* Flash: 0 wait states */ | ||
83 | CSCR1 = 0x00000180; /* LCD: 0 wait states */ | ||
84 | DCR = (0x8000 | DEFAULT_REFRESH_TIMER); /* Refresh timer */ | ||
85 | cpu_frequency = CPUFREQ_DEFAULT; | ||
86 | IDECONFIG1 = 0x106000 | (1 << 10); /* BUFEN2 enable + CS2Pre/CS2Post */ | ||
87 | IDECONFIG2 = 0x40000 | (0 << 8); /* TA enable + CS2wait */ | ||
88 | break; | ||
89 | } | ||
90 | } | ||